204 lines
6.1 KiB
C
204 lines
6.1 KiB
C
/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2021, Ha Thach (tinyusb.org)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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#ifndef _DWC2_STM32_H_
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#define _DWC2_STM32_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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// EP_MAX : Max number of bi-directional endpoints including EP0
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// EP_FIFO_SIZE : Size of dedicated USB SRAM
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#if CFG_TUSB_MCU == OPT_MCU_STM32F1
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#include "stm32f1xx.h"
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#define EP_MAX_FS 4
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#define EP_FIFO_SIZE_FS 1280
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#elif CFG_TUSB_MCU == OPT_MCU_STM32F2
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#include "stm32f2xx.h"
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#define EP_MAX_FS USB_OTG_FS_MAX_IN_ENDPOINTS
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#define EP_FIFO_SIZE_FS USB_OTG_FS_TOTAL_FIFO_SIZE
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#elif CFG_TUSB_MCU == OPT_MCU_STM32F4
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#include "stm32f4xx.h"
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#define EP_MAX_FS USB_OTG_FS_MAX_IN_ENDPOINTS
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#define EP_FIFO_SIZE_FS USB_OTG_FS_TOTAL_FIFO_SIZE
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#define EP_MAX_HS USB_OTG_HS_MAX_IN_ENDPOINTS
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#define EP_FIFO_SIZE_HS USB_OTG_HS_TOTAL_FIFO_SIZE
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#elif CFG_TUSB_MCU == OPT_MCU_STM32H7
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#include "stm32h7xx.h"
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#define EP_MAX_FS 9
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#define EP_FIFO_SIZE_FS 4096
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#define EP_MAX_HS 9
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#define EP_FIFO_SIZE_HS 4096
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#elif CFG_TUSB_MCU == OPT_MCU_STM32F7
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#include "stm32f7xx.h"
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#define EP_MAX_FS 6
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#define EP_FIFO_SIZE_FS 1280
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#define EP_MAX_HS 9
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#define EP_FIFO_SIZE_HS 4096
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#elif CFG_TUSB_MCU == OPT_MCU_STM32L4
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#include "stm32l4xx.h"
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#define EP_MAX_FS 6
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#define EP_FIFO_SIZE_FS 1280
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#else
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#error "Unsupported MCUs"
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#endif
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// On STM32 we associate Port0 to OTG_FS, and Port1 to OTG_HS
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#if TUD_OPT_RHPORT == 0
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#define DWC2_REG_BASE USB_OTG_FS_PERIPH_BASE
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#define DWC2_EP_MAX EP_MAX_FS
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#define DWC2_EP_FIFO_SIZE EP_FIFO_SIZE_FS
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#define RHPORT_IRQn OTG_FS_IRQn
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#else
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#define DWC2_REG_BASE USB_OTG_HS_PERIPH_BASE
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#define DWC2_EP_MAX EP_MAX_HS
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#define DWC2_EP_FIFO_SIZE EP_FIFO_SIZE_HS
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#define RHPORT_IRQn OTG_HS_IRQn
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#endif
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extern uint32_t SystemCoreClock;
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TU_ATTR_ALWAYS_INLINE
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static inline void dwc2_dcd_int_enable(uint8_t rhport)
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{
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(void) rhport;
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NVIC_EnableIRQ(RHPORT_IRQn);
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}
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TU_ATTR_ALWAYS_INLINE
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static inline void dwc2_dcd_int_disable (uint8_t rhport)
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{
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(void) rhport;
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NVIC_DisableIRQ(RHPORT_IRQn);
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}
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TU_ATTR_ALWAYS_INLINE
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static inline void dwc2_remote_wakeup_delay(void)
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{
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// try to delay for 1 ms
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uint32_t count = SystemCoreClock / 1000;
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while ( count-- ) __NOP();
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}
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// Set turn-around timeout according to link speed
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static inline void dwc2_set_turnaround(dwc2_regs_t * dwc2, tusb_speed_t speed)
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{
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dwc2->gusbcfg &= ~GUSBCFG_TRDT;
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if ( speed == TUSB_SPEED_HIGH )
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{
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// Use fixed 0x09 for Highspeed
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dwc2->gusbcfg |= (0x09 << GUSBCFG_TRDT_Pos);
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}
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else
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{
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// Turnaround timeout depends on the MCU clock
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uint32_t turnaround;
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if ( SystemCoreClock >= 32000000U )
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turnaround = 0x6U;
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else if ( SystemCoreClock >= 27500000U )
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turnaround = 0x7U;
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else if ( SystemCoreClock >= 24000000U )
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turnaround = 0x8U;
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else if ( SystemCoreClock >= 21800000U )
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turnaround = 0x9U;
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else if ( SystemCoreClock >= 20000000U )
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turnaround = 0xAU;
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else if ( SystemCoreClock >= 18500000U )
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turnaround = 0xBU;
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else if ( SystemCoreClock >= 17200000U )
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turnaround = 0xCU;
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else if ( SystemCoreClock >= 16000000U )
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turnaround = 0xDU;
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else if ( SystemCoreClock >= 15000000U )
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turnaround = 0xEU;
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else
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turnaround = 0xFU;
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// Fullspeed depends on MCU clocks, but we will use 0x06 for 32+ Mhz
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dwc2->gusbcfg |= (turnaround << GUSBCFG_TRDT_Pos);
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}
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}
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#if defined(USB_HS_PHYC)
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static inline void dwc2_stm32_utmi_phy_init(dwc2_regs_t * dwc2)
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{
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USB_HS_PHYC_GlobalTypeDef *usb_hs_phyc = (USB_HS_PHYC_GlobalTypeDef*) USB_HS_PHYC_CONTROLLER_BASE;
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// Enable UTMI HS PHY
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dwc2->stm32_gccfg |= STM32_GCCFG_PHYHSEN;
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// Enable LDO
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usb_hs_phyc->USB_HS_PHYC_LDO |= USB_HS_PHYC_LDO_ENABLE;
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// Wait until LDO ready
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while ( 0 == (usb_hs_phyc->USB_HS_PHYC_LDO & USB_HS_PHYC_LDO_STATUS) ) {}
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uint32_t phyc_pll = 0;
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// TODO Try to get HSE_VALUE from registers instead of depending CFLAGS
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switch ( HSE_VALUE )
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{
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case 12000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12MHZ ; break;
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case 12500000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_12_5MHZ ; break;
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case 16000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_16MHZ ; break;
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case 24000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_24MHZ ; break;
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case 25000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_25MHZ ; break;
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case 32000000: phyc_pll = USB_HS_PHYC_PLL1_PLLSEL_Msk ; break; // Value not defined in header
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default:
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TU_ASSERT(false, );
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}
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usb_hs_phyc->USB_HS_PHYC_PLL = phyc_pll;
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// Control the tuning interface of the High Speed PHY
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// Use magic value (USB_HS_PHYC_TUNE_VALUE) from ST driver
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usb_hs_phyc->USB_HS_PHYC_TUNE |= 0x00000F13U;
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// Enable PLL internal PHY
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usb_hs_phyc->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN;
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// Original ST code has 2 ms delay for PLL stabilization.
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// Primitive test shows that more than 10 USB un/replug cycle showed no error with enumeration
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}
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* _DWC2_STM32_H_ */
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