68 lines
1.8 KiB
Makefile
68 lines
1.8 KiB
Makefile
UF2_FAMILY_ID = 0x2abc77ec
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SDK_DIR = hw/mcu/nxp/mcux-sdk
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include $(TOP)/$(BOARD_PATH)/board.mk
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# Default to Highspeed PORT1
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PORT ?= 1
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CFLAGS += \
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-flto \
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-DBOARD_TUD_RHPORT=$(PORT) \
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# mcu driver cause following warnings
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CFLAGS += -Wno-error=unused-parameter -Wno-error=old-style-declaration
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LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
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# All source paths should be relative to the top level.
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LD_FILE ?= $(SDK_DIR)/devices/$(MCU_VARIANT)/gcc/$(MCU_CORE)_flash.ld
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# TinyUSB: Port0 is chipidea FS, Port1 is chipidea HS
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ifeq ($(PORT), 1)
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$(info "PORT1 High Speed")
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CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
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SRC_C += src/portable/chipidea/ci_hs/dcd_ci_hs.c
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else
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$(info "PORT0 Full Speed")
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CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
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SRC_C += src/portable/chipidea/ci_fs/dcd_ci_fs.c
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endif
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SRC_C += \
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$(SDK_DIR)/devices/$(MCU_VARIANT)/system_$(MCU_CORE).c \
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$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_clock.c \
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$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers/fsl_reset.c \
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${SDK_DIR}/drivers/gpio/fsl_gpio.c \
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${SDK_DIR}/drivers/lpuart/fsl_lpuart.c \
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${SDK_DIR}/drivers/common/fsl_common_arm.c\
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hw/bsp/mcx/drivers/spc/fsl_spc.c
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# fsl_lpflexcomm for MCXN9
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ifeq ($(MCU_VARIANT), MCXN947)
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SRC_C += ${SDK_DIR}/drivers/lpflexcomm/fsl_lpflexcomm.c
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endif
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# fsl_spc for MCXNA15
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ifeq ($(MCU_VARIANT), MCXA153)
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endif
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INC += \
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$(TOP)/$(BOARD_PATH) \
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$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
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$(TOP)/$(SDK_DIR)/devices/$(MCU_VARIANT) \
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$(TOP)/$(SDK_DIR)/devices/$(MCU_VARIANT)/drivers \
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$(TOP)/$(SDK_DIR)/drivers/ \
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$(TOP)/$(SDK_DIR)/drivers/lpuart \
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$(TOP)/$(SDK_DIR)/drivers/lpflexcomm \
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$(TOP)/$(SDK_DIR)/drivers/common\
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$(TOP)/$(SDK_DIR)/drivers/gpio\
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$(TOP)/$(SDK_DIR)/drivers/port\
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$(TOP)/hw/bsp/mcx/drivers/spc
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SRC_S += $(SDK_DIR)/devices/$(MCU_VARIANT)/gcc/startup_$(MCU_CORE).S
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