777 lines
21 KiB
C
777 lines
21 KiB
C
/********************************** (C) COPYRIGHT *******************************
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* File Name : system_ch32v30x.c
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* Author : WCH
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* Version : V1.0.0
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* Date : 2021/06/06
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* Description : CH32V30x Device Peripheral Access Layer System Source File.
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* For HSE = 8Mhz
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* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
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* SPDX-License-Identifier: Apache-2.0
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*********************************************************************************/
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#include "ch32v30x.h"
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/*
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* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
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* reset the HSI is used as SYSCLK source).
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* If none of the define below is enabled, the HSI is used as System clock source.
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*/
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// #define SYSCLK_FREQ_HSE HSE_VALUE
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/* #define SYSCLK_FREQ_24MHz 24000000 */
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//#define SYSCLK_FREQ_48MHz 48000000
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/* #define SYSCLK_FREQ_56MHz 56000000 */
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//#define SYSCLK_FREQ_72MHz 72000000
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//#define SYSCLK_FREQ_96MHz 96000000
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//#define SYSCLK_FREQ_120MHz 120000000
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#define SYSCLK_FREQ_144MHz 144000000
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/* Clock Definitions */
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#ifdef SYSCLK_FREQ_HSE
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uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /* System Clock Frequency (Core Clock) */
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#elif defined SYSCLK_FREQ_24MHz
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uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /* System Clock Frequency (Core Clock) */
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#elif defined SYSCLK_FREQ_48MHz
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uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /* System Clock Frequency (Core Clock) */
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#elif defined SYSCLK_FREQ_56MHz
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uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /* System Clock Frequency (Core Clock) */
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#elif defined SYSCLK_FREQ_72MHz
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uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /* System Clock Frequency (Core Clock) */
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#elif defined SYSCLK_FREQ_96MHz
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uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz; /* System Clock Frequency (Core Clock) */
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#elif defined SYSCLK_FREQ_120MHz
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uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz; /* System Clock Frequency (Core Clock) */
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#elif defined SYSCLK_FREQ_144MHz
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uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz; /* System Clock Frequency (Core Clock) */
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#else /* HSI Selected as System Clock source */
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uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */
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#endif
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__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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/* system_private_function_proto_types */
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static void SetSysClock(void);
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#ifdef SYSCLK_FREQ_HSE
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static void SetSysClockToHSE(void);
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#elif defined SYSCLK_FREQ_24MHz
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static void SetSysClockTo24(void);
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#elif defined SYSCLK_FREQ_48MHz
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static void SetSysClockTo48(void);
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#elif defined SYSCLK_FREQ_56MHz
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static void SetSysClockTo56(void);
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#elif defined SYSCLK_FREQ_72MHz
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static void SetSysClockTo72(void);
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#elif defined SYSCLK_FREQ_96MHz
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static void SetSysClockTo96(void);
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#elif defined SYSCLK_FREQ_120MHz
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static void SetSysClockTo120(void);
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#elif defined SYSCLK_FREQ_144MHz
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static void SetSysClockTo144(void);
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#endif
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/*********************************************************************
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* @fn SystemInit
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*
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* @brief Setup the microcontroller system Initialize the Embedded Flash Interface,
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* the PLL and update the SystemCoreClock variable.
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*
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* @return none
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*/
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void SystemInit (void)
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{
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RCC->CTLR |= (uint32_t)0x00000001;
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#ifdef CH32V30x_D8C
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RCC->CFGR0 &= (uint32_t)0xF8FF0000;
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#else
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RCC->CFGR0 &= (uint32_t)0xF0FF0000;
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#endif
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RCC->CTLR &= (uint32_t)0xFEF6FFFF;
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RCC->CTLR &= (uint32_t)0xFFFBFFFF;
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RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
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#ifdef CH32V30x_D8C
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RCC->CTLR &= (uint32_t)0xEBFFFFFF;
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RCC->INTR = 0x00FF0000;
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RCC->CFGR2 = 0x00000000;
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#else
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RCC->INTR = 0x009F0000;
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#endif
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SetSysClock();
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}
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/*********************************************************************
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* @fn SystemCoreClockUpdate
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*
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* @brief Update SystemCoreClock variable according to Clock Register Values.
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*
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* @return none
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*/
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void SystemCoreClockUpdate (void)
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{
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uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0;
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tmp = RCC->CFGR0 & RCC_SWS;
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switch (tmp)
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{
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case 0x00:
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SystemCoreClock = HSI_VALUE;
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break;
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case 0x04:
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SystemCoreClock = HSE_VALUE;
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break;
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case 0x08:
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pllmull = RCC->CFGR0 & RCC_PLLMULL;
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pllsource = RCC->CFGR0 & RCC_PLLSRC;
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pllmull = ( pllmull >> 18) + 2;
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#ifdef CH32V30x_D8
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if(pllmull == 17) pllmull = 18;
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#else
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if(pllmull == 2) pllmull = 18;
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if(pllmull == 15){
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pllmull = 13; /* *6.5 */
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Pll_6_5 = 1;
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}
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if(pllmull == 16) pllmull = 15;
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if(pllmull == 17) pllmull = 16;
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#endif
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if (pllsource == 0x00)
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{
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SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
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}
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else
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{
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if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET)
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{
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SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
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}
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else
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{
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SystemCoreClock = HSE_VALUE * pllmull;
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}
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}
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if(Pll_6_5 == 1) SystemCoreClock = (SystemCoreClock / 2);
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break;
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default:
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SystemCoreClock = HSI_VALUE;
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break;
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}
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tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
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SystemCoreClock >>= tmp;
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}
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/*********************************************************************
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* @fn SetSysClock
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*
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* @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
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*
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* @return none
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*/
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static void SetSysClock(void)
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{
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#ifdef SYSCLK_FREQ_HSE
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SetSysClockToHSE();
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#elif defined SYSCLK_FREQ_24MHz
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SetSysClockTo24();
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#elif defined SYSCLK_FREQ_48MHz
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SetSysClockTo48();
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#elif defined SYSCLK_FREQ_56MHz
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SetSysClockTo56();
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#elif defined SYSCLK_FREQ_72MHz
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SetSysClockTo72();
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#elif defined SYSCLK_FREQ_96MHz
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SetSysClockTo96();
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#elif defined SYSCLK_FREQ_120MHz
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SetSysClockTo120();
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#elif defined SYSCLK_FREQ_144MHz
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SetSysClockTo144();
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#endif
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/* If none of the define above is enabled, the HSI is used as System clock
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* source (default after reset)
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*/
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}
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#ifdef SYSCLK_FREQ_HSE
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/*********************************************************************
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* @fn SetSysClockToHSE
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*
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* @brief Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
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*
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* @return none
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*/
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static void SetSysClockToHSE(void)
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{
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__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
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RCC->CTLR |= ((uint32_t)RCC_HSEON);
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/* Wait till HSE is ready and if Time out is reached exit */
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do
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{
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HSEStatus = RCC->CTLR & RCC_HSERDY;
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StartUpCounter++;
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} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
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if ((RCC->CTLR & RCC_HSERDY) != RESET)
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{
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HSEStatus = (uint32_t)0x01;
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}
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else
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{
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HSEStatus = (uint32_t)0x00;
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}
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if (HSEStatus == (uint32_t)0x01)
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{
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/* HCLK = SYSCLK */
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RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
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/* PCLK2 = HCLK */
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RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
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/* PCLK1 = HCLK */
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RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
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/* Select HSE as system clock source */
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RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
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RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;
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/* Wait till HSE is used as system clock source */
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while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04)
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{
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}
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}
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else
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{
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/* If HSE fails to start-up, the application will have wrong clock
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* configuration. User can add here some code to deal with this error
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*/
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}
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}
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#elif defined SYSCLK_FREQ_24MHz
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/*********************************************************************
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* @fn SetSysClockTo24
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*
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* @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
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*
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* @return none
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*/
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static void SetSysClockTo24(void)
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{
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__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
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RCC->CTLR |= ((uint32_t)RCC_HSEON);
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/* Wait till HSE is ready and if Time out is reached exit */
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do
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{
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HSEStatus = RCC->CTLR & RCC_HSERDY;
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StartUpCounter++;
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} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
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if ((RCC->CTLR & RCC_HSERDY) != RESET)
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{
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HSEStatus = (uint32_t)0x01;
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}
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else
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{
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HSEStatus = (uint32_t)0x00;
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}
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if (HSEStatus == (uint32_t)0x01)
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{
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/* HCLK = SYSCLK */
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RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
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/* PCLK2 = HCLK */
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RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
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/* PCLK1 = HCLK */
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RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
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RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
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#ifdef CH32V30x_D8
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RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL3);
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#else
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RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL3_EXTEN);
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#endif
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/* Enable PLL */
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RCC->CTLR |= RCC_PLLON;
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/* Wait till PLL is ready */
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while((RCC->CTLR & RCC_PLLRDY) == 0)
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{
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}
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/* Select PLL as system clock source */
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RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
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RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
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/* Wait till PLL is used as system clock source */
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while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
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{
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}
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}
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else
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{
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/* If HSE fails to start-up, the application will have wrong clock
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* configuration. User can add here some code to deal with this error
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*/
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}
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}
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#elif defined SYSCLK_FREQ_48MHz
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/*********************************************************************
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* @fn SetSysClockTo48
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*
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* @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
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*
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* @return none
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*/
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static void SetSysClockTo48(void)
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{
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__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
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RCC->CTLR |= ((uint32_t)RCC_HSEON);
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/* Wait till HSE is ready and if Time out is reached exit */
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do
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{
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HSEStatus = RCC->CTLR & RCC_HSERDY;
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StartUpCounter++;
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} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
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if ((RCC->CTLR & RCC_HSERDY) != RESET)
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{
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HSEStatus = (uint32_t)0x01;
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}
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else
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{
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HSEStatus = (uint32_t)0x00;
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}
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if (HSEStatus == (uint32_t)0x01)
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{
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/* HCLK = SYSCLK */
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RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
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/* PCLK2 = HCLK */
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RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
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/* PCLK1 = HCLK */
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RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
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/* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
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RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
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#ifdef CH32V30x_D8
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RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6);
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#else
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RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6_EXTEN);
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#endif
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/* Enable PLL */
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RCC->CTLR |= RCC_PLLON;
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/* Wait till PLL is ready */
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while((RCC->CTLR & RCC_PLLRDY) == 0)
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{
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}
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/* Select PLL as system clock source */
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RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
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RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
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/* Wait till PLL is used as system clock source */
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while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
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{
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}
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}
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else
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{
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/*
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* If HSE fails to start-up, the application will have wrong clock
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* configuration. User can add here some code to deal with this error
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*/
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}
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}
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#elif defined SYSCLK_FREQ_56MHz
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/*********************************************************************
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* @fn SetSysClockTo56
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*
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* @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
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*
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* @return none
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*/
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static void SetSysClockTo56(void)
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{
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__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
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RCC->CTLR |= ((uint32_t)RCC_HSEON);
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/* Wait till HSE is ready and if Time out is reached exit */
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do
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{
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HSEStatus = RCC->CTLR & RCC_HSERDY;
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StartUpCounter++;
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} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
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if ((RCC->CTLR & RCC_HSERDY) != RESET)
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{
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HSEStatus = (uint32_t)0x01;
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}
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else
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{
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HSEStatus = (uint32_t)0x00;
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}
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if (HSEStatus == (uint32_t)0x01)
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{
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/* HCLK = SYSCLK */
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RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
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/* PCLK2 = HCLK */
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RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
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/* PCLK1 = HCLK */
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RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
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/* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
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RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
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#ifdef CH32V30x_D8
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RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7);
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#else
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RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7_EXTEN);
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#endif
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/* Enable PLL */
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RCC->CTLR |= RCC_PLLON;
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/* Wait till PLL is ready */
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while((RCC->CTLR & RCC_PLLRDY) == 0)
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{
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}
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/* Select PLL as system clock source */
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RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
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RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
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/* Wait till PLL is used as system clock source */
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while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
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{
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}
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}
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else
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{
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/*
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* If HSE fails to start-up, the application will have wrong clock
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* configuration. User can add here some code to deal with this error
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*/
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}
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}
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#elif defined SYSCLK_FREQ_72MHz
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/*********************************************************************
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* @fn SetSysClockTo72
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*
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* @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
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*
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* @return none
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*/
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static void SetSysClockTo72(void)
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{
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__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
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RCC->CTLR |= ((uint32_t)RCC_HSEON);
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/* Wait till HSE is ready and if Time out is reached exit */
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do
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{
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HSEStatus = RCC->CTLR & RCC_HSERDY;
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StartUpCounter++;
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} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
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if ((RCC->CTLR & RCC_HSERDY) != RESET)
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{
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HSEStatus = (uint32_t)0x01;
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|
}
|
|
else
|
|
{
|
|
HSEStatus = (uint32_t)0x00;
|
|
}
|
|
|
|
if (HSEStatus == (uint32_t)0x01)
|
|
{
|
|
/* HCLK = SYSCLK */
|
|
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
|
/* PCLK2 = HCLK */
|
|
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
|
/* PCLK1 = HCLK */
|
|
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
|
|
|
/* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
|
|
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
|
|
RCC_PLLMULL));
|
|
|
|
#ifdef CH32V30x_D8
|
|
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9);
|
|
#else
|
|
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9_EXTEN);
|
|
#endif
|
|
|
|
/* Enable PLL */
|
|
RCC->CTLR |= RCC_PLLON;
|
|
/* Wait till PLL is ready */
|
|
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
|
{
|
|
}
|
|
/* Select PLL as system clock source */
|
|
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
|
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
|
/* Wait till PLL is used as system clock source */
|
|
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
|
{
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/*
|
|
* If HSE fails to start-up, the application will have wrong clock
|
|
* configuration. User can add here some code to deal with this error
|
|
*/
|
|
}
|
|
}
|
|
|
|
|
|
#elif defined SYSCLK_FREQ_96MHz
|
|
|
|
/*********************************************************************
|
|
* @fn SetSysClockTo96
|
|
*
|
|
* @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
|
*
|
|
* @return none
|
|
*/
|
|
static void SetSysClockTo96(void)
|
|
{
|
|
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
|
|
|
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
|
|
|
/* Wait till HSE is ready and if Time out is reached exit */
|
|
do
|
|
{
|
|
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
|
StartUpCounter++;
|
|
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
|
|
|
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
|
{
|
|
HSEStatus = (uint32_t)0x01;
|
|
}
|
|
else
|
|
{
|
|
HSEStatus = (uint32_t)0x00;
|
|
}
|
|
|
|
if (HSEStatus == (uint32_t)0x01)
|
|
{
|
|
/* HCLK = SYSCLK */
|
|
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
|
/* PCLK2 = HCLK */
|
|
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
|
/* PCLK1 = HCLK */
|
|
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
|
|
|
/* PLL configuration: PLLCLK = HSE * 12 = 96 MHz */
|
|
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
|
|
RCC_PLLMULL));
|
|
|
|
#ifdef CH32V30x_D8
|
|
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12);
|
|
#else
|
|
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12_EXTEN);
|
|
#endif
|
|
|
|
/* Enable PLL */
|
|
RCC->CTLR |= RCC_PLLON;
|
|
/* Wait till PLL is ready */
|
|
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
|
{
|
|
}
|
|
/* Select PLL as system clock source */
|
|
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
|
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
|
/* Wait till PLL is used as system clock source */
|
|
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
|
{
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/*
|
|
* If HSE fails to start-up, the application will have wrong clock
|
|
* configuration. User can add here some code to deal with this error
|
|
*/
|
|
}
|
|
}
|
|
|
|
|
|
#elif defined SYSCLK_FREQ_120MHz
|
|
|
|
/*********************************************************************
|
|
* @fn SetSysClockTo120
|
|
*
|
|
* @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
|
*
|
|
* @return none
|
|
*/
|
|
static void SetSysClockTo120(void)
|
|
{
|
|
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
|
|
|
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
|
|
|
/* Wait till HSE is ready and if Time out is reached exit */
|
|
do
|
|
{
|
|
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
|
StartUpCounter++;
|
|
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
|
|
|
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
|
{
|
|
HSEStatus = (uint32_t)0x01;
|
|
}
|
|
else
|
|
{
|
|
HSEStatus = (uint32_t)0x00;
|
|
}
|
|
|
|
if (HSEStatus == (uint32_t)0x01)
|
|
{
|
|
/* HCLK = SYSCLK */
|
|
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
|
/* PCLK2 = HCLK */
|
|
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
|
/* PCLK1 = HCLK */
|
|
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
|
|
|
/* PLL configuration: PLLCLK = HSE * 15 = 120 MHz */
|
|
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
|
|
RCC_PLLMULL));
|
|
|
|
#ifdef CH32V30x_D8
|
|
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15);
|
|
#else
|
|
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15_EXTEN);
|
|
#endif
|
|
|
|
/* Enable PLL */
|
|
RCC->CTLR |= RCC_PLLON;
|
|
/* Wait till PLL is ready */
|
|
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
|
{
|
|
}
|
|
/* Select PLL as system clock source */
|
|
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
|
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
|
/* Wait till PLL is used as system clock source */
|
|
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
|
{
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/*
|
|
* If HSE fails to start-up, the application will have wrong clock
|
|
* configuration. User can add here some code to deal with this error
|
|
*/
|
|
}
|
|
}
|
|
|
|
|
|
#elif defined SYSCLK_FREQ_144MHz
|
|
|
|
/*********************************************************************
|
|
* @fn SetSysClockTo144
|
|
*
|
|
* @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
|
*
|
|
* @return none
|
|
*/
|
|
static void SetSysClockTo144(void)
|
|
{
|
|
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
|
|
|
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
|
|
|
/* Wait till HSE is ready and if Time out is reached exit */
|
|
do
|
|
{
|
|
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
|
StartUpCounter++;
|
|
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
|
|
|
if ((RCC->CTLR & RCC_HSERDY) != RESET)
|
|
{
|
|
HSEStatus = (uint32_t)0x01;
|
|
}
|
|
else
|
|
{
|
|
HSEStatus = (uint32_t)0x00;
|
|
}
|
|
|
|
if (HSEStatus == (uint32_t)0x01)
|
|
{
|
|
/* HCLK = SYSCLK */
|
|
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
|
/* PCLK2 = HCLK */
|
|
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
|
/* PCLK1 = HCLK */
|
|
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
|
|
|
/* PLL configuration: PLLCLK = HSE * 18 = 144 MHz */
|
|
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
|
|
RCC_PLLMULL));
|
|
|
|
#ifdef CH32V30x_D8
|
|
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18);
|
|
#else
|
|
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18_EXTEN);
|
|
#endif
|
|
|
|
/* Enable PLL */
|
|
RCC->CTLR |= RCC_PLLON;
|
|
/* Wait till PLL is ready */
|
|
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
|
{
|
|
}
|
|
/* Select PLL as system clock source */
|
|
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
|
|
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
|
/* Wait till PLL is used as system clock source */
|
|
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
|
{
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/*
|
|
* If HSE fails to start-up, the application will have wrong clock
|
|
* configuration. User can add here some code to deal with this error
|
|
*/
|
|
}
|
|
}
|
|
|
|
|
|
#endif
|