239 lines
7.9 KiB
C
239 lines
7.9 KiB
C
/*
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* @brief LPC13xx PMU chip driver
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2013
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __PMU_13XX_H_
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#define __PMU_13XX_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @defgroup PMU_13XX CHIP: LPC13xx Power Management Unit block driver
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* @ingroup CHIP_13XX_Drivers
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* @{
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*/
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/**
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* @brief LPC13xx Power Management Unit register block structure
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*/
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typedef struct {
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__IO uint32_t PCON; /*!< Offset: 0x000 Power control Register (R/W) */
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__IO uint32_t GPREG[4]; /*!< Offset: 0x004 General purpose Registers 0..3 (R/W) */
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__IO uint32_t DPDCTRL; /*!< Offset: 0x014 Deep power-down control register (R/W) */
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} LPC_PMU_T;
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/**
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* @brief LPC13xx low power mode type definitions
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*/
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typedef enum CHIP_PMU_MCUPOWER {
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PMU_MCU_SLEEP = 0, /*!< Sleep mode */
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PMU_MCU_DEEP_SLEEP, /*!< Deep Sleep mode */
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#if defined(CHIP_LPC1347)
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PMU_MCU_POWER_DOWN, /*!< Power down mode */
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#endif
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PMU_MCU_DEEP_PWRDOWN /*!< Deep power down mode */
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} CHIP_PMU_MCUPOWER_T;
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/**
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* PMU PCON register bit fields & masks
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*/
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#define PMU_PCON_PM_SLEEP (0x0) /*!< ARM WFI enter sleep mode */
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#if defined(CHIP_LPC1347)
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#define PMU_PCON_PM_DEEPSLEEP (0x1) /*!< ARM WFI enter Deep-sleep mode */
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#define PMU_PCON_PM_POWERDOWN (0x2) /*!< ARM WFI enter Power-down mode */
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#define PMU_PCON_PM_DEEPPOWERDOWN (0x3) /*!< ARM WFI enter Deep Power-down mode */
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#elif defined(CHIP_LPC1343)
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#define PMU_PCON_PM_DEEPPOWERDOWN (0x2) /*!< ARM WFI enter Deep Power-down mode */
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#endif
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#define PMU_PCON_NODPD (1 << 3) /*!< Disable deep power-down mode */
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#define PMU_PCON_SLEEPFLAG (1 << 8) /*!< Sleep mode flag */
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#define PMU_PCON_DPDFLAG (1 << 11) /*!< Deep power-down flag */
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/**
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* PMU DPDCTRL register bit fields & masks
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*/
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#define PMU_DPDCTRL_WAKEUPPHYS (1 << 10) /** Enable wake-up pin hysteresis */
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/**
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* @brief Write a value to a GPREG register
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* @param pPMU : Pointer to PMU register block
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* @param regIndex : Register index to write to, must be 0..3
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* @param value : Value to write
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* @return None
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*/
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STATIC INLINE void Chip_PMU_WriteGPREG(LPC_PMU_T *pPMU, uint8_t regIndex, uint32_t value)
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{
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pPMU->GPREG[regIndex] = value;
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}
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/**
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* @brief Read a value to a GPREG register
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* @param pPMU : Pointer to PMU register block
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* @param regIndex : Register index to read from, must be 0..3
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* @return Value read from the GPREG register
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*/
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STATIC INLINE uint32_t Chip_PMU_ReadGPREG(LPC_PMU_T *pPMU, uint8_t regIndex)
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{
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return pPMU->GPREG[regIndex];
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}
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/**
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* @brief Enter MCU Sleep mode
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* @param pPMU : Pointer to PMU register block
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* @return None
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* @note The sleep mode affects the ARM Cortex-M0+ core only. Peripherals
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* and memories are active.
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*/
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void Chip_PMU_SleepState(LPC_PMU_T *pPMU);
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/**
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* @brief Enter MCU Deep Sleep mode
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* @param pPMU : Pointer to PMU register block
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* @return None
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* @note In Deep-sleep mode, the peripherals receive no internal clocks.
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* The flash is in stand-by mode. The SRAM memory and all peripheral registers
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* as well as the processor maintain their internal states. The WWDT, WKT,
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* and BOD can remain active to wake up the system on an interrupt.
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*/
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void Chip_PMU_DeepSleepState(LPC_PMU_T *pPMU);
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/**
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* @brief Enter MCU Power down mode
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* @param pPMU : Pointer to PMU register block
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* @return None
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* @note In Power-down mode, the peripherals receive no internal clocks.
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* The internal SRAM memory and all peripheral registers as well as the
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* processor maintain their internal states. The flash memory is powered
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* down. The WWDT, WKT, and BOD can remain active to wake up the system
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* on an interrupt.
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*/
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#if defined(CHIP_LPC1347)
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void Chip_PMU_PowerDownState(LPC_PMU_T *pPMU);
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#endif
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/**
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* @brief Enter MCU Deep Power down mode
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* @param pPMU : Pointer to PMU register block
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* @return None
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* @note For maximal power savings, the entire system is shut down
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* except for the general purpose registers in the PMU and the self
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* wake-up timer. Only the general purpose registers in the PMU maintain
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* their internal states. The part can wake up on a pulse on the WAKEUP
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* pin or when the self wake-up timer times out. On wake-up, the part
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* reboots.
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*/
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void Chip_PMU_DeepPowerDownState(LPC_PMU_T *pPMU);
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/**
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* @brief Place the MCU in a low power state
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* @param pPMU : Pointer to PMU register block
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* @param SleepMode : Sleep mode
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* @return None
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*/
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void Chip_PMU_Sleep(LPC_PMU_T *pPMU, CHIP_PMU_MCUPOWER_T SleepMode);
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/**
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* @brief Disables deep power-down mode
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* @param pPMU : Pointer to PMU register block
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* @return None
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* @note Calling this functions prevents entry to Deep power-down
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* mode. Once set, this can only be cleared by power-on reset.
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*/
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STATIC INLINE void Chip_PMU_DisableDeepPowerDown(LPC_PMU_T *pPMU)
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{
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pPMU->PCON |= PMU_PCON_NODPD;
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}
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/**
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* @brief Returns sleep/power-down flags
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* @param pPMU : Pointer to PMU register block
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* @return Or'ed values of PMU_PCON_SLEEPFLAG and PMU_PCON_DPDFLAG
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* @note These indicate that the PMU is setup for entry into a low
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* power state on the next WFI() instruction.
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*/
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STATIC INLINE uint32_t Chip_PMU_GetSleepFlags(LPC_PMU_T *pPMU)
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{
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return pPMU->PCON & (PMU_PCON_SLEEPFLAG | PMU_PCON_DPDFLAG);
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}
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/**
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* @brief Clears sleep/power-down flags
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* @param pPMU : Pointer to PMU register block
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* @param flags : Or'ed value of PMU_PCON_SLEEPFLAG and PMU_PCON_DPDFLAG
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* @return Nothing
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* @note Use this function to clear a low power state prior to calling
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* WFI().
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*/
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STATIC INLINE void Chip_PMU_ClearSleepFlags(LPC_PMU_T *pPMU, uint32_t flags)
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{
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pPMU->PCON &= ~flags;
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}
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/**
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* @brief Sets deep power-down functions
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* @param pPMU : Pointer to PMU register block
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* @param flags : Or'ed value of PMU_DPDCTRL_* values
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* @return Nothing
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* @note Some of these functions may need to be set prior to going
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* into a low power mode. Note that some calls to this function enable
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* functions while others disable it based on the PMU_DPDCTRL_*
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* definitions.
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*/
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STATIC INLINE void Chip_PMU_SetPowerDownControl(LPC_PMU_T *pPMU, uint32_t flags)
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{
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pPMU->DPDCTRL |= flags;
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}
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/**
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* @brief Cleats deep power-down functions
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* @param pPMU : Pointer to PMU register block
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* @param flags : Or'ed value of PMU_DPDCTRL_* values
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* @return Nothing
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* @note Some of these functions may need to be cleared prior to going
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* into a low power mode. Note that some calls to this function enable
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* functions while others disable it based on the PMU_DPDCTRL_*
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* definitions.
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*/
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STATIC INLINE void Chip_PMU_ClearPowerDownControl(LPC_PMU_T *pPMU, uint32_t flags)
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{
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pPMU->DPDCTRL &= ~flags;
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}
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __PMU_13XX_H_ */
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