278 lines
9.8 KiB
C
278 lines
9.8 KiB
C
/**********************************************************************
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* $Id$ lpc43xx_cgu.h 2011-06-02
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*//**
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* @file llpc43xx_cgu.h
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* @brief Contains all macro definitions and function prototypes
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* support for Clock Generation and Clock Control firmware
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* library on lpc43xx
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* @version 1.0
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* @date 02. June. 2011
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* @author NXP MCU SW Application Team
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*
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* Copyright(C) 2011, NXP Semiconductor
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* All rights reserved.
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*
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***********************************************************************
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* products. This software is supplied "AS IS" without any warranties.
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* NXP Semiconductors assumes no responsibility or liability for the
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* use of the software, conveys no license or title under any patent,
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* copyright, or mask work right to the product. NXP Semiconductors
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* reserves the right to make changes in the software without
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* notification. NXP Semiconductors also make no representation or
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* warranty that such application will be suitable for the specified
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* use without further testing or modification.
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors<72>
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* relevant copyright in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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**********************************************************************/
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/* Peripheral group ----------------------------------------------------------- */
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/** @defgroup CGU CGU (Clock Generation Unit)
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* @ingroup LPC4300CMSIS_FwLib_Drivers
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* @{
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*/
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#ifndef lpc43xx_CGU_H_
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#define lpc43xx_CGU_H_
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/* Includes ------------------------------------------------------------------- */
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#include "LPC43xx.h"
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#include "lpc_types.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/* Private Macros -------------------------------------------------------------- */
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/** @defgroup CGU_Private_Macros CGU Private Macros
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* @{
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*/
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/** Branch clocks from CGU_BASE_SAFE */
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#define CGU_ENTITY_NONE CGU_ENTITY_NUM
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/** Check bit at specific position is clear or not */
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#define ISBITCLR(x,bit) ((x&(1<<bit))^(1<<bit))
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/** Check bit at specific position is set or not */
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#define ISBITSET(x,bit) (x&(1<<bit))
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/** Set mask */
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#define ISMASKSET(x,mask) (x&mask)
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/** CGU number of clock source */
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#define CGU_CLKSRC_NUM (CGU_CLKSRC_IDIVE+1)
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/*********************************************************************//**
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* Macro defines for CGU control mask bit definitions
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**********************************************************************/
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/** CGU control enable mask bit */
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#define CGU_CTRL_EN_MASK 1
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/** CGU control clock-source mask bit */
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#define CGU_CTRL_SRC_MASK (0xF<<24)
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/** CGU control auto block mask bit */
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#define CGU_CTRL_AUTOBLOCK_MASK (1<<11)
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/*********************************************************************//**
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* Macro defines for CGU PLL1 mask bit definitions
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**********************************************************************/
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/** CGU PLL1 feedback select mask bit */
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#define CGU_PLL1_FBSEL_MASK (1<<6)
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/** CGU PLL1 Input clock bypass control mask bit */
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#define CGU_PLL1_BYPASS_MASK (1<<1)
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/** CGU PLL1 direct CCO output mask bit */
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#define CGU_PLL1_DIRECT_MASK (1<<7)
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/**
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* @}
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*/
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/* Public Types --------------------------------------------------------------- */
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/** @defgroup CGU_Public_Types CGU Public Types
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* @{
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*/
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/*********************************************************************//**
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* @brief CGU enumeration
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**********************************************************************/
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/*
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* @brief CGU clock source enumerate definition
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*/
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typedef enum {
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/* Clock Source */
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CGU_CLKSRC_32KHZ_OSC = 0, /**< 32KHz oscillator clock source */
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CGU_CLKSRC_IRC, /**< IRC 12 Mhz clock source */
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CGU_CLKSRC_ENET_RX_CLK, /**< Ethernet receive clock source */
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CGU_CLKSRC_ENET_TX_CLK, /**< Ethernet transmit clock source */
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CGU_CLKSRC_GP_CLKIN, /**< General purpose clock source */
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CGU_CLKSRC_TCK, /**< TCK clock source */
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CGU_CLKSRC_XTAL_OSC, /**< Crystal oscillator clock source*/
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CGU_CLKSRC_PLL0, /**< PLL0 (USB0) clock source */
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CGU_CLKSRC_PLL0_AUDIO,
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CGU_CLKSRC_PLL1, /**< PLL1 clock source */
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CGU_CLKSRC_IDIVA = CGU_CLKSRC_PLL1 + 3, /**< IDIVA clock source */
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CGU_CLKSRC_IDIVB, /**< IDIVB clock source */
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CGU_CLKSRC_IDIVC, /**< IDIVC clock source */
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CGU_CLKSRC_IDIVD, /**< IDIVD clock source */
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CGU_CLKSRC_IDIVE, /**< IDIVE clock source */
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/* Base */
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CGU_BASE_SAFE, /**< Base save clock (always on) for WDT */
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CGU_BASE_USB0, /**< USB0 base clock */
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CGU_BASE_PERIPH, /** Peripheral bus (SGPIO) */
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CGU_BASE_USB1, /**< USB1 base clock */
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CGU_BASE_M4, /**< ARM Cortex-M4 Core base clock */
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CGU_BASE_SPIFI, /**< SPIFI base clock */
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CGU_BASE_PHY_RX = CGU_BASE_SPIFI + 2, /**< Ethernet PHY Rx base clock */
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CGU_BASE_PHY_TX, /**< Ethernet PHY Tx base clock */
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CGU_BASE_APB1, /**< APB peripheral block #1 base clock */
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CGU_BASE_APB3, /**< APB peripheral block #3 base clock */
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CGU_BASE_LCD, /**< LCD base clock */
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CGU_BASE_ENET_CSR,
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CGU_BASE_SDIO, /**< SDIO base clock */
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CGU_BASE_SSP0, /**< SSP0 base clock */
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CGU_BASE_SSP1, /**< SSP1 base clock */
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CGU_BASE_UART0, /**< UART0 base clock */
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CGU_BASE_UART1, /**< UART1 base clock */
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CGU_BASE_UART2, /**< UART2 base clock */
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CGU_BASE_UART3, /**< UART3 base clock */
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CGU_BASE_CLKOUT, /**< CLKOUT base clock */
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CGU_BASE_APLL = CGU_BASE_CLKOUT + 5,
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CGU_BASE_OUT0,
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CGU_BASE_OUT1,
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CGU_ENTITY_NUM /**< Number or clock source entity */
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} CGU_ENTITY_T;
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/*
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* @brief CGU PPL0 mode enumerate definition
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*/
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typedef enum {
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CGU_PLL0_MODE_1d = 0,
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CGU_PLL0_MODE_1c,
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CGU_PLL0_MODE_1b,
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CGU_PLL0_MODE_1a
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}CGU_PLL0_MODE;
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/*
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* @brief CGU peripheral enumerate definition
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*/
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typedef enum {
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CGU_PERIPHERAL_ADC0 = 0, /**< ADC0 */
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CGU_PERIPHERAL_ADC1, /**< ADC1 */
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CGU_PERIPHERAL_AES, /**< AES */
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// CGU_PERIPHERAL_ALARMTIMER_CGU_RGU_RTC_WIC,
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CGU_PERIPHERAL_APB1_BUS, /**< APB1 bus */
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CGU_PERIPHERAL_APB3_BUS, /**< APB3 bus */
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CGU_PERIPHERAL_CAN, /**< CAN */
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CGU_PERIPHERAL_CREG, /**< CREG */
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CGU_PERIPHERAL_DAC, /**< DAC */
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CGU_PERIPHERAL_DMA, /**< DMA */
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CGU_PERIPHERAL_EMC, /**< EMC */
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CGU_PERIPHERAL_ETHERNET, /**< Ethernet */
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CGU_PERIPHERAL_ETHERNET_TX, //HIDE /**< Ethernet transmit */
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CGU_PERIPHERAL_GPIO, /**< GPIO */
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CGU_PERIPHERAL_I2C0, /**< I2C0 */
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CGU_PERIPHERAL_I2C1, /**< I2C1 */
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CGU_PERIPHERAL_I2S, /**< I2S */
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CGU_PERIPHERAL_LCD, /**< LCD */
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CGU_PERIPHERAL_M4CORE, /**< ARM Cortex-M4 Core */
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CGU_PERIPHERAL_M4_BUS, /**< ARM Cortex-M4 Bus */
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CGU_PERIPHERAL_MOTOCON, /**< Motor Control */
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CGU_PERIPHERAL_QEI, /**< QEI */
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CGU_PERIPHERAL_RITIMER, /**< RIT Timer */
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CGU_PERIPHERAL_SCT, /**< SCT */
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CGU_PERIPHERAL_SCU, /**< SCU */
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CGU_PERIPHERAL_SDIO, /**< SDIO */
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CGU_PERIPHERAL_SPIFI, /**< SPIFI */
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CGU_PERIPHERAL_SSP0, /**< SSP0 */
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CGU_PERIPHERAL_SSP1, /**< SSP1 */
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CGU_PERIPHERAL_TIMER0, /**< TIMER 0 */
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CGU_PERIPHERAL_TIMER1, /**< TIMER 1 */
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CGU_PERIPHERAL_TIMER2, /**< TIMER 2 */
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CGU_PERIPHERAL_TIMER3, /**< TIMER 3 */
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CGU_PERIPHERAL_UART0, /**< UART0 */
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CGU_PERIPHERAL_UART1, /**< UART1 */
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CGU_PERIPHERAL_UART2, /**< UART2 */
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CGU_PERIPHERAL_UART3, /**< UART3 */
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CGU_PERIPHERAL_USB0, /**< USB0 */
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CGU_PERIPHERAL_USB1, /**< USB1 */
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CGU_PERIPHERAL_WWDT, /**< WWDT */
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CGU_PERIPHERAL_NUM
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} CGU_PERIPHERAL_T;
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/**
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* @brief CGU error status enumerate definition
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*/
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typedef enum {
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CGU_ERROR_SUCCESS = 0,
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CGU_ERROR_CONNECT_TOGETHER,
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CGU_ERROR_INVALID_ENTITY,
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CGU_ERROR_INVALID_CLOCK_SOURCE,
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CGU_ERROR_INVALID_PARAM,
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CGU_ERROR_FREQ_OUTOF_RANGE
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} CGU_ERROR;
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/********************************************************************//**
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* @brief CGU structure definitions
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**********************************************************************/
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/*
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* @brief CGU peripheral clock structure
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*/
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typedef struct {
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uint8_t RegBaseEntity; /**< Base register address */
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uint16_t RegBranchOffset; /**< Branch register offset */
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uint8_t PerBaseEntity; /**< Base peripheral address */
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uint16_t PerBranchOffset; /**< Base peripheral offset */
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uint8_t next; /**< Pointer to next structure */
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} CGU_PERIPHERAL_S;
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/**
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* @}
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*/
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/* Public Functions ----------------------------------------------------------- */
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/** @defgroup CGU_Public_Functions CGU Public Functions
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* @{
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*/
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/** Clock generate initialize/de-initialize */
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uint32_t CGU_Init(void);
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uint32_t CGU_DeInit(void);
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/** Clock Generator and Clock Control */
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uint32_t CGU_ConfigPWR (CGU_PERIPHERAL_T PPType, FunctionalState en);
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uint32_t CGU_GetPCLKFrequency (CGU_PERIPHERAL_T Clock);
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/** Clock Source and Base Clock operation */
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uint32_t CGU_SetXTALOSC(uint32_t ClockFrequency);
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uint32_t CGU_SetDIV(CGU_ENTITY_T SelectDivider, uint32_t divisor);
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uint32_t CGU_SetPLL0(void);
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uint32_t CGU_SetPLL0audio(void);
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uint32_t CGU_SetPLL1(uint32_t mult);
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uint32_t CGU_EnableEntity(CGU_ENTITY_T ClockEntity, uint32_t en);
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uint32_t CGU_EntityConnect(CGU_ENTITY_T ClockSource, CGU_ENTITY_T ClockEntity);
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uint32_t CGU_GetBaseStatus(CGU_ENTITY_T Base);
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void CGU_UpdateClock(void);
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uint32_t CGU_RealFrequencyCompare(CGU_ENTITY_T Clock, CGU_ENTITY_T CompareToClock, uint32_t *m, uint32_t *d);
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* lpc43xx_CGU_H_ */
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/**
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* @}
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*/
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