216 lines
5.6 KiB
C
216 lines
5.6 KiB
C
/* Auto-generated config file hpl_usart_config.h */
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#ifndef HPL_USART_CONFIG_H
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#define HPL_USART_CONFIG_H
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// <<< Use Configuration Wizard in Context Menu >>>
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#include <peripheral_clk_config.h>
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#ifndef CONF_USART_1_ENABLE
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#define CONF_USART_1_ENABLE 1
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#endif
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// <h> Basic Configuration
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// <o> Frame parity
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// <0x0=>Even parity
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// <0x1=>Odd parity
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// <0x2=>Parity forced to 0
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// <0x3=>Parity forced to 1
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// <0x4=>No parity
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// <i> Parity bit mode for USART frame
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// <id> usart_parity
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#ifndef CONF_USART_1_PARITY
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#define CONF_USART_1_PARITY 0x4
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#endif
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// <o> Character Size
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// <0x0=>5 bits
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// <0x1=>6 bits
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// <0x2=>7 bits
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// <0x3=>8 bits
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// <i> Data character size in USART frame
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// <id> usart_character_size
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#ifndef CONF_USART_1_CHSIZE
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#define CONF_USART_1_CHSIZE 0x3
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#endif
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// <o> Stop Bit
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// <0=>1 stop bit
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// <1=>1.5 stop bits
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// <2=>2 stop bits
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// <i> Number of stop bits in USART frame
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// <id> usart_stop_bit
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#ifndef CONF_USART_1_SBMODE
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#define CONF_USART_1_SBMODE 0
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#endif
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// <o> Clock Output Select
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// <0=>The USART does not drive the SCK pin
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// <1=>The USART drives the SCK pin if USCLKS does not select the external clock SCK
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// <i> Clock Output Select in USART sck, if in usrt master mode, please drive SCK.
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// <id> usart_clock_output_select
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#ifndef CONF_USART_1_CLKO
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#define CONF_USART_1_CLKO 0
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#endif
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// <o> Baud rate <1-3000000>
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// <i> USART baud rate setting
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// <id> usart_baud_rate
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#ifndef CONF_USART_1_BAUD
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#define CONF_USART_1_BAUD 9600
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#endif
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// </h>
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// <e> Advanced configuration
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// <id> usart_advanced
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#ifndef CONF_USART_1_ADVANCED_CONFIG
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#define CONF_USART_1_ADVANCED_CONFIG 0
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#endif
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// <o> Channel Mode
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// <0=>Normal Mode
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// <1=>Automatic Echo
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// <2=>Local Loopback
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// <3=>Remote Loopback
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// <i> Channel mode in USART frame
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// <id> usart_channel_mode
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#ifndef CONF_USART_1_CHMODE
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#define CONF_USART_1_CHMODE 0
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#endif
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// <q> 9 bits character enable
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// <i> Enable 9 bits character, this has high priority than 5/6/7/8 bits.
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// <id> usart_9bits_enable
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#ifndef CONF_USART_1_MODE9
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#define CONF_USART_1_MODE9 0
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#endif
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// <o> Variable Sync
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// <0=>User defined configuration
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// <1=>sync field is updated when a character is written into US_THR
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// <i> Variable Synchronization of Command/Data Sync Start Frarm Delimiter
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// <id> variable_sync
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#ifndef CONF_USART_1_VAR_SYNC
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#define CONF_USART_1_VAR_SYNC 0
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#endif
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// <o> Oversampling Mode
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// <0=>16 Oversampling
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// <1=>8 Oversampling
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// <i> Oversampling Mode in UART mode
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// <id> usart__oversampling_mode
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#ifndef CONF_USART_1_OVER
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#define CONF_USART_1_OVER 0
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#endif
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// <o> Inhibit Non Ack
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// <0=>The NACK is generated
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// <1=>The NACK is not generated
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// <i> Inhibit Non Acknowledge
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// <id> usart__inack
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#ifndef CONF_USART_1_INACK
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#define CONF_USART_1_INACK 1
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#endif
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// <o> Disable Successive NACK
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// <0=>NACK is sent on the ISO line as soon as a parity error occurs
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// <1=>Many parity errors generate a NACK on the ISO line
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// <i> Disable Successive NACK
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// <id> usart_dsnack
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#ifndef CONF_USART_1_DSNACK
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#define CONF_USART_1_DSNACK 0
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#endif
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// <o> Inverted Data
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// <0=>Data isn't inverted, nomal mode
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// <1=>Data is inverted
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// <i> Inverted Data
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// <id> usart_invdata
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#ifndef CONF_USART_1_INVDATA
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#define CONF_USART_1_INVDATA 0
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#endif
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// <o> Maximum Number of Automatic Iteration <0-7>
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// <i> Defines the maximum number of iterations in mode ISO7816, protocol T = 0.
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// <id> usart_max_iteration
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#ifndef CONF_USART_1_MAX_ITERATION
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#define CONF_USART_1_MAX_ITERATION 0
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#endif
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// <q> Receive Line Filter enable
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// <i> whether the USART filters the receive line using a three-sample filter
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// <id> usart_receive_filter_enable
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#ifndef CONF_USART_1_FILTER
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#define CONF_USART_1_FILTER 0
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#endif
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// <q> Manchester Encoder/Decoder Enable
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// <i> whether the USART Manchester Encoder/Decoder
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// <id> usart_manchester_filter_enable
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#ifndef CONF_USART_1_MAN
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#define CONF_USART_1_MAN 0
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#endif
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// <o> Manchester Synchronization Mode
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// <0=>The Manchester start bit is a 0 to 1 transition
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// <1=>The Manchester start bit is a 1 to 0 transition
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// <i> Manchester Synchronization Mode
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// <id> usart_manchester_synchronization_mode
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#ifndef CONF_USART_1_MODSYNC
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#define CONF_USART_1_MODSYNC 0
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#endif
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// <o> Start Frame Delimiter Selector
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// <0=>Start frame delimiter is COMMAND or DATA SYNC
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// <1=>Start frame delimiter is one bit
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// <i> Start Frame Delimiter Selector
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// <id> usart_start_frame_delimiter
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#ifndef CONF_USART_1_ONEBIT
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#define CONF_USART_1_ONEBIT 0
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#endif
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// <o> Fractional Part <0-7>
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// <i> Fractional part of the baud rate if baud rate generator is in fractional mode
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// <id> usart_arch_fractional
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#ifndef CONF_USART_1_FRACTIONAL
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#define CONF_USART_1_FRACTIONAL 0x0
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#endif
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// <o> Data Order
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// <0=>LSB is transmitted first
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// <1=>MSB is transmitted first
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// <i> Data order of the data bits in the frame
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// <id> usart_arch_msbf
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#ifndef CONF_USART_1_MSBF
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#define CONF_USART_1_MSBF 0
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#endif
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// </e>
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#define CONF_USART_1_MODE 0x0
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// Calculate BAUD register value in UART mode
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#if CONF_USART1_CK_SRC < 3
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#ifndef CONF_USART_1_BAUD_CD
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#define CONF_USART_1_BAUD_CD ((CONF_USART1_FREQUENCY) / CONF_USART_1_BAUD / 8 / (2 - CONF_USART_1_OVER))
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#endif
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#ifndef CONF_USART_1_BAUD_FP
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#define CONF_USART_1_BAUD_FP \
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((CONF_USART1_FREQUENCY) / CONF_USART_1_BAUD / (2 - CONF_USART_1_OVER) - 8 * CONF_USART_1_BAUD_CD)
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#endif
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#elif CONF_USART1_CK_SRC == 3
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// No division is active. The value written in US_BRGR has no effect.
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#ifndef CONF_USART_1_BAUD_CD
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#define CONF_USART_1_BAUD_CD 1
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#endif
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#ifndef CONF_USART_1_BAUD_FP
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#define CONF_USART_1_BAUD_FP 1
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#endif
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#endif
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// <<< end of configuration section >>>
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#endif // HPL_USART_CONFIG_H
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