145 lines
7.7 KiB
C
145 lines
7.7 KiB
C
/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/***********************************************************************************************************************
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* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
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* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
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**********************************************************************************************************************/
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/* clang-format off */
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/*
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* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!GlobalInfo
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product: Pins v15.0
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processor: MCXA156
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package_id: MCXA156VLL
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mcu_data: ksdk2_0
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processor_version: 0.15.0
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
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*/
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/* clang-format on */
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#include "fsl_common.h"
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#include "fsl_port.h"
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#include "pin_mux.h"
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/* FUNCTION ************************************************************************************************************
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*
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* Function Name : BOARD_InitBootPins
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* Description : Calls initialization functions.
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*
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* END ****************************************************************************************************************/
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void BOARD_InitBootPins(void)
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{
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BOARD_InitPins();
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}
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/* clang-format off */
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/*
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* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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BOARD_InitPins:
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- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
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- pin_list:
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- {pin_num: '78', peripheral: LPUART0, signal: RX, pin_signal: P0_2/TDO/SWO/LPUART0_RXD/LPSPI0_SCK/CT0_MAT0/UTICK_CAP0/FLEXIO0_D2, slew_rate: fast, open_drain: disable,
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drive_strength: low, pull_select: up, pull_enable: enable, input_buffer: enable, invert_input: normal}
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- {pin_num: '79', peripheral: LPUART0, signal: TX, pin_signal: P0_3/TDI/LPUART0_TXD/LPSPI0_SDO/CT0_MAT1/UTICK_CAP1/FLEXIO0_D3/CMP0_OUT, slew_rate: fast, open_drain: disable,
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drive_strength: low, pull_select: up, pull_enable: enable, input_buffer: enable, invert_input: normal}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
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*/
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/* clang-format on */
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/* FUNCTION ************************************************************************************************************
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*
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* Function Name : BOARD_InitPins
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* Description : Configures pin routing and optionally pin electrical features.
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*
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* END ****************************************************************************************************************/
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void BOARD_InitPins(void)
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{
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RESET_PeripheralReset(kLPUART0_RST_SHIFT_RSTn);
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CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u);
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CLOCK_AttachClk(kFRO12M_to_LPUART0);
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/* GPIO3: Peripheral clock is enabled */
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CLOCK_EnableClock(kCLOCK_GateGPIO3);
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/* PORT3: Peripheral clock is enabled */
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CLOCK_EnableClock(kCLOCK_GatePORT3);
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/* GPIO3 peripheral is released from reset */
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RESET_ReleasePeripheralReset(kGPIO3_RST_SHIFT_RSTn);
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/* PORT3 peripheral is released from reset */
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RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn);
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/* GPIO3: Peripheral clock is enabled */
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CLOCK_EnableClock(kCLOCK_GateGPIO0);
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/* PORT3: Peripheral clock is enabled */
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CLOCK_EnableClock(kCLOCK_GatePORT0);
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/* GPIO3 peripheral is released from reset */
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RESET_ReleasePeripheralReset(kGPIO0_RST_SHIFT_RSTn);
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/* PORT3 peripheral is released from reset */
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RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn);
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/* PORT0: Peripheral clock is enabled */
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CLOCK_EnableClock(kCLOCK_GatePORT0);
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/* LPUART0 peripheral is released from reset */
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RESET_ReleasePeripheralReset(kLPUART0_RST_SHIFT_RSTn);
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/* PORT0 peripheral is released from reset */
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RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn);
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const port_pin_config_t port0_2_pin78_config = {/* Internal pull-up resistor is enabled */
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kPORT_PullUp,
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/* Low internal pull resistor value is selected. */
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kPORT_LowPullResistor,
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/* Fast slew rate is configured */
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kPORT_FastSlewRate,
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/* Passive input filter is disabled */
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kPORT_PassiveFilterDisable,
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/* Open drain output is disabled */
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kPORT_OpenDrainDisable,
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/* Low drive strength is configured */
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kPORT_LowDriveStrength,
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/* Normal drive strength is configured */
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kPORT_NormalDriveStrength,
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/* Pin is configured as LPUART0_RXD */
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kPORT_MuxAlt2,
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/* Digital input enabled */
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kPORT_InputBufferEnable,
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/* Digital input is not inverted */
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kPORT_InputNormal,
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/* Pin Control Register fields [15:0] are not locked */
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kPORT_UnlockRegister};
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/* PORT0_2 (pin 78) is configured as LPUART0_RXD */
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PORT_SetPinConfig(PORT0, 2U, &port0_2_pin78_config);
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const port_pin_config_t port0_3_pin79_config = {/* Internal pull-up resistor is enabled */
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kPORT_PullUp,
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/* Low internal pull resistor value is selected. */
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kPORT_LowPullResistor,
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/* Fast slew rate is configured */
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kPORT_FastSlewRate,
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/* Passive input filter is disabled */
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kPORT_PassiveFilterDisable,
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/* Open drain output is disabled */
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kPORT_OpenDrainDisable,
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/* Low drive strength is configured */
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kPORT_LowDriveStrength,
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/* Normal drive strength is configured */
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kPORT_NormalDriveStrength,
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/* Pin is configured as LPUART0_TXD */
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kPORT_MuxAlt2,
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/* Digital input enabled */
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kPORT_InputBufferEnable,
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/* Digital input is not inverted */
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kPORT_InputNormal,
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/* Pin Control Register fields [15:0] are not locked */
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kPORT_UnlockRegister};
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/* PORT0_3 (pin 79) is configured as LPUART0_TXD */
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PORT_SetPinConfig(PORT0, 3U, &port0_3_pin79_config);
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}
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/***********************************************************************************************************************
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* EOF
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**********************************************************************************************************************/
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