453ea39865
fix binary.h compiler specific add hal_init code to reset & set usbmode --> able to get USB ISR remove const qualifier from return function of - get_operational_register - get_period_frame_list - get_async_head - get_period_head - get_control_qhd add stub for - hcd_port_connect_status - hcd_port_speed
347 lines
13 KiB
ArmAsm
347 lines
13 KiB
ArmAsm
;/***********************************************************************
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; * $Id: startup_LPC43xx.s 6473 2011-02-16 17:40:54Z nxp27266 $
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; *
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; * Project: LPC43xx CMSIS Package
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; *
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; * Description: Cortex-M3 Core Device Startup File for the NXP LPC43xx
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; * Device Series.
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; *
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; * Copyright(C) 2011, NXP Semiconductor
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; * All rights reserved.
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; *
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; * modified by KEIL
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; ***********************************************************************
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; * Software that is described herein is for illustrative purposes only
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; * which provides customers with programming information regarding the
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; * products. This software is supplied "AS IS" without any warranties.
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; * NXP Semiconductors assumes no responsibility or liability for the
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; * use of the software, conveys no license or title under any patent,
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; * copyright, or mask work right to the product. NXP Semiconductors
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; * reserves the right to make changes in the software without
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; * notification. NXP Semiconductors also make no representation or
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; * warranty that such application will be suitable for the specified
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; * use without further testing or modification.
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; **********************************************************************/
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; <h> Stack Configuration
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; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Stack_Size EQU 0x00000400
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Stack_Mem SPACE Stack_Size
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__initial_sp
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; <h> Heap Configuration
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; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Heap_Size EQU 0x00000200
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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Sign_Value EQU 0x5A5A5A5A
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__Vectors DCD __initial_sp ; 0 Top of Stack
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DCD Reset_Handler ; 1 Reset Handler
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DCD NMI_Handler ; 2 NMI Handler
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DCD HardFault_Handler ; 3 Hard Fault Handler
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DCD MemManage_Handler ; 4 MPU Fault Handler
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DCD BusFault_Handler ; 5 Bus Fault Handler
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DCD UsageFault_Handler ; 6 Usage Fault Handler
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DCD Sign_Value ; 7 Reserved
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DCD 0 ; 8 Reserved
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DCD 0 ; 9 Reserved
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DCD 0 ; 10 Reserved
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DCD SVC_Handler ; 11 SVCall Handler
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DCD DebugMon_Handler ; 12 Debug Monitor Handler
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DCD 0 ; 13 Reserved
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DCD PendSV_Handler ; 14 PendSV Handler
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DCD SysTick_Handler ; 15 SysTick Handler
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; External Interrupts
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DCD DAC_IRQHandler ; 16 D/A Converter
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DCD M0CORE_IRQHandler ; 17 M0 Core
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DCD DMA_IRQHandler ; 18 General Purpose DMA
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DCD EZH_IRQHandler ; 19 EZH/EDM
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DCD FLASH_EEPROM_IRQHandler ; 20 Reserved for Typhoon
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DCD ETH_IRQHandler ; 21 Ethernet
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DCD SDIO_IRQHandler ; 22 SD/MMC
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DCD LCD_IRQHandler ; 23 LCD
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DCD USB0_IRQHandler ; 24 USB0
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DCD USB1_IRQHandler ; 25 USB1
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DCD SCT_IRQHandler ; 26 State Configurable Timer
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DCD RIT_IRQHandler ; 27 Repetitive Interrupt Timer
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DCD TIMER0_IRQHandler ; 28 Timer0
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DCD TIMER1_IRQHandler ; 29 Timer1
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DCD TIMER2_IRQHandler ; 30 Timer2
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DCD TIMER3_IRQHandler ; 31 Timer3
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DCD MCPWM_IRQHandler ; 32 Motor Control PWM
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DCD ADC0_IRQHandler ; 33 A/D Converter 0
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DCD I2C0_IRQHandler ; 34 I2C0
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DCD I2C1_IRQHandler ; 35 I2C1
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DCD SPI_IRQHandler ; 36 SPI
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DCD ADC1_IRQHandler ; 37 A/D Converter 1
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DCD SSP0_IRQHandler ; 38 SSP0
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DCD SSP1_IRQHandler ; 39 SSP1
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DCD UART0_IRQHandler ; 40 UART0
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DCD UART1_IRQHandler ; 41 UART1
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DCD UART2_IRQHandler ; 42 UART2
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DCD UART3_IRQHandler ; 43 UART3
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DCD I2S0_IRQHandler ; 44 I2S0
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DCD I2S1_IRQHandler ; 45 I2S1
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DCD SPIFI_IRQHandler ; 46 SPI Flash Interface
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DCD SGPIO_IRQHandler ; 47 SGPIO
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DCD GPIO0_IRQHandler ; 48 GPIO0
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DCD GPIO1_IRQHandler ; 49 GPIO1
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DCD GPIO2_IRQHandler ; 50 GPIO2
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DCD GPIO3_IRQHandler ; 51 GPIO3
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DCD GPIO4_IRQHandler ; 52 GPIO4
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DCD GPIO5_IRQHandler ; 53 GPIO5
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DCD GPIO6_IRQHandler ; 54 GPIO6
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DCD GPIO7_IRQHandler ; 55 GPIO7
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DCD GINT0_IRQHandler ; 56 GINT0
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DCD GINT1_IRQHandler ; 57 GINT1
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DCD EVRT_IRQHandler ; 58 Event Router
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DCD CAN1_IRQHandler ; 59 C_CAN1
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DCD 0 ; 60 Reserved
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DCD VADC_IRQHandler ; 61 VADC
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DCD ATIMER_IRQHandler ; 62 ATIMER
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DCD RTC_IRQHandler ; 63 RTC
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DCD 0 ; 64 Reserved
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DCD WDT_IRQHandler ; 65 WDT
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DCD M0s_IRQHandler ; 66 M0s
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DCD CAN0_IRQHandler ; 67 C_CAN0
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DCD QEI_IRQHandler ; 68 QEI
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;CRP address at offset 0x2FC relative to the BOOT Bank address
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IF :LNOT::DEF:NO_CRP
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SPACE (0x2FC - (. - __Vectors))
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; EXPORT CRP_Key
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CRP_Key DCD 0xFFFFFFFF
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; 0xFFFFFFFF => CRP Disabled
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; 0x12345678 => CRP Level 1
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; 0x87654321 => CRP Level 2
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; 0x43218765 => CRP Level 3 (ARE YOU SURE?)
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; 0x4E697370 => NO ISP (ARE YOU SURE?)
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ENDIF
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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MemManage_Handler\
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PROC
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EXPORT MemManage_Handler [WEAK]
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B .
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ENDP
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BusFault_Handler\
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PROC
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EXPORT BusFault_Handler [WEAK]
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B .
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ENDP
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UsageFault_Handler\
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PROC
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EXPORT UsageFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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DebugMon_Handler\
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PROC
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EXPORT DebugMon_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT DAC_IRQHandler [WEAK]
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EXPORT M0CORE_IRQHandler [WEAK]
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EXPORT DMA_IRQHandler [WEAK]
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EXPORT EZH_IRQHandler [WEAK]
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EXPORT FLASH_EEPROM_IRQHandler [WEAK]
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EXPORT ETH_IRQHandler [WEAK]
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EXPORT SDIO_IRQHandler [WEAK]
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EXPORT LCD_IRQHandler [WEAK]
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EXPORT USB0_IRQHandler [WEAK]
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EXPORT USB1_IRQHandler [WEAK]
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EXPORT SCT_IRQHandler [WEAK]
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EXPORT RIT_IRQHandler [WEAK]
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EXPORT TIMER0_IRQHandler [WEAK]
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EXPORT TIMER1_IRQHandler [WEAK]
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EXPORT TIMER2_IRQHandler [WEAK]
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EXPORT TIMER3_IRQHandler [WEAK]
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EXPORT MCPWM_IRQHandler [WEAK]
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EXPORT ADC0_IRQHandler [WEAK]
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EXPORT I2C0_IRQHandler [WEAK]
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EXPORT I2C1_IRQHandler [WEAK]
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EXPORT SPI_IRQHandler [WEAK]
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EXPORT ADC1_IRQHandler [WEAK]
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EXPORT SSP0_IRQHandler [WEAK]
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EXPORT SSP1_IRQHandler [WEAK]
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EXPORT UART0_IRQHandler [WEAK]
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EXPORT UART1_IRQHandler [WEAK]
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EXPORT UART2_IRQHandler [WEAK]
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EXPORT UART3_IRQHandler [WEAK]
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EXPORT I2S0_IRQHandler [WEAK]
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EXPORT I2S1_IRQHandler [WEAK]
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EXPORT SPIFI_IRQHandler [WEAK]
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EXPORT SGPIO_IRQHandler [WEAK]
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EXPORT GPIO0_IRQHandler [WEAK]
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EXPORT GPIO1_IRQHandler [WEAK]
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EXPORT GPIO2_IRQHandler [WEAK]
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EXPORT GPIO3_IRQHandler [WEAK]
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EXPORT GPIO4_IRQHandler [WEAK]
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EXPORT GPIO5_IRQHandler [WEAK]
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EXPORT GPIO6_IRQHandler [WEAK]
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EXPORT GPIO7_IRQHandler [WEAK]
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EXPORT GINT0_IRQHandler [WEAK]
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EXPORT GINT1_IRQHandler [WEAK]
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EXPORT EVRT_IRQHandler [WEAK]
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EXPORT CAN1_IRQHandler [WEAK]
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EXPORT VADC_IRQHandler [WEAK]
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EXPORT ATIMER_IRQHandler [WEAK]
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EXPORT RTC_IRQHandler [WEAK]
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EXPORT WDT_IRQHandler [WEAK]
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EXPORT M0s_IRQHandler [WEAK]
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EXPORT CAN0_IRQHandler [WEAK]
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EXPORT QEI_IRQHandler [WEAK]
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DAC_IRQHandler
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M0CORE_IRQHandler
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DMA_IRQHandler
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EZH_IRQHandler
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FLASH_EEPROM_IRQHandler
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ETH_IRQHandler
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SDIO_IRQHandler
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LCD_IRQHandler
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USB0_IRQHandler
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USB1_IRQHandler
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SCT_IRQHandler
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RIT_IRQHandler
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TIMER0_IRQHandler
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TIMER1_IRQHandler
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TIMER2_IRQHandler
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TIMER3_IRQHandler
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MCPWM_IRQHandler
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ADC0_IRQHandler
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I2C0_IRQHandler
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I2C1_IRQHandler
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SPI_IRQHandler
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ADC1_IRQHandler
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SSP0_IRQHandler
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SSP1_IRQHandler
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UART0_IRQHandler
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UART1_IRQHandler
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UART2_IRQHandler
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UART3_IRQHandler
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I2S0_IRQHandler
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I2S1_IRQHandler
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SPIFI_IRQHandler
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SGPIO_IRQHandler
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GPIO0_IRQHandler
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GPIO1_IRQHandler
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GPIO2_IRQHandler
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GPIO3_IRQHandler
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GPIO4_IRQHandler
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GPIO5_IRQHandler
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GPIO6_IRQHandler
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GPIO7_IRQHandler
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GINT0_IRQHandler
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GINT1_IRQHandler
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EVRT_IRQHandler
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CAN1_IRQHandler
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VADC_IRQHandler
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ATIMER_IRQHandler
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RTC_IRQHandler
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WDT_IRQHandler
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M0s_IRQHandler
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CAN0_IRQHandler
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QEI_IRQHandler
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B .
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ENDP
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ALIGN
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; User Initial Stack & Heap
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IF :DEF:__MICROLIB
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EXPORT __initial_sp
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EXPORT __heap_base
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EXPORT __heap_limit
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ELSE
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IMPORT __use_two_region_memory
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EXPORT __user_initial_stackheap
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__user_initial_stackheap
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LDR R0, = Heap_Mem
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LDR R1, =(Stack_Mem + Stack_Size)
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LDR R2, = (Heap_Mem + Heap_Size)
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LDR R3, = Stack_Mem
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BX LR
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ALIGN
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ENDIF
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AREA |.text|,CODE, READONLY
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getPC PROC
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EXPORT getPC
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MOV R0,LR
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BX LR
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ENDP
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END
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