419 lines
14 KiB
C
419 lines
14 KiB
C
/*
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* @brief LPC11u6x I2C driver
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2013
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __I2CM_11U6X_H_
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#define __I2CM_11U6X_H_
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#include "i2c_common_11u6x.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @defgroup I2CM_11U6X CHIP: LPC11u6x I2C master-only driver
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* @ingroup I2C_11U6X
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* This driver only works in master mode. To describe the I2C transactions
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* following symbols are used in driver documentation.
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*
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* Key to symbols
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* ==============
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* S (1 bit) : Start bit
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* P (1 bit) : Stop bit
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* Rd/Wr (1 bit) : Read/Write bit. Rd equals 1, Wr equals 0.
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* A, NA (1 bit) : Acknowledge and Not-Acknowledge bit.
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* Addr (7 bits): I2C 7 bit address. Note that this can be expanded as usual to
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* get a 10 bit I2C address.
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* Data (8 bits): A plain data byte. Sometimes, I write DataLow, DataHigh
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* for 16 bit data.
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* [..]: Data sent by I2C device, as opposed to data sent by the host adapter.
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* @{
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*/
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/** I2CM_11U6X_OPTIONS_TYPES I2C master transfer options
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* @{
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*/
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/** Ignore NACK during data transfer. By default transfer is aborted. */
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#define I2CM_XFER_OPTION_IGNORE_NACK 0x01
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/** ACK last byte received. By default we NACK last byte we receive per I2C spec. */
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#define I2CM_XFER_OPTION_LAST_RX_ACK 0x02
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/**
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* @}
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*/
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/** I2CM_11U6X_STATUS_TYPES I2C master transfer status types
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* @{
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*/
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#define I2CM_STATUS_OK 0x00 /*!< Requested Request was executed successfully. */
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#define I2CM_STATUS_ERROR 0x01 /*!< Unknown error condition. */
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#define I2CM_STATUS_NAK 0x02 /*!< No acknowledgement received from slave. */
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#define I2CM_STATUS_BUS_ERROR 0x03 /*!< I2C bus error */
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#define I2CM_STATUS_SLAVE_NAK 0x04 /*!< No device responded for given slave address during SLA+W or SLA+R */
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#define I2CM_STATUS_ARBLOST 0x05 /*!< Arbitration lost. */
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#define I2CM_STATUS_BUSY 0xFF /*!< I2C transmistter is busy. */
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/**
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* @}
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*/
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/**
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* @brief Master transfer data structure definitions
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*/
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typedef struct {
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uint8_t slaveAddr; /*!< 7-bit I2C Slave address */
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uint8_t options; /*!< Options for transfer*/
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uint16_t status; /*!< Status of the current I2C transfer */
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uint16_t txSz; /*!< Number of bytes in transmit array,
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if 0 only receive transfer will be carried on */
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uint16_t rxSz; /*!< Number of bytes to received,
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if 0 only transmission we be carried on */
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const uint8_t *txBuff; /*!< Pointer to array of bytes to be transmitted */
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uint8_t *rxBuff; /*!< Pointer memory where bytes received from I2C be stored */
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} I2CM_XFER_T;
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/**
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* @brief Initialize I2C Interface
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* @param pI2C : Pointer to selected I2C peripheral
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* @return Nothing
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* @note This function enables the I2C clock.
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*/
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void Chip_I2CM_Init(LPC_I2C_T *pI2C);
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/**
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* @brief Shutdown I2C Interface
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* @param pI2C : Pointer to selected I2C peripheral
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* @return Nothing
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* @note This function disables the I2C clock.
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*/
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void Chip_I2CM_DeInit(LPC_I2C_T *pI2C);
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/**
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* @brief Sets HIGH and LOW duty cycle registers
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* @param pI2C : Pointer to selected I2C peripheral
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* @param sclH : Number of I2C_PCLK cycles for the SCL HIGH time.
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* @param sclL : Number of I2C_PCLK cycles for the SCL LOW time.
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* @return Nothing
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* @note The frequency is determined by the following formula (I2C_PCLK
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* is the frequency of the peripheral I2C clock): <br>
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* I2C_bitFrequency = (I2C_PCLK)/(sclH + sclL);
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*/
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static INLINE void Chip_I2CM_SetDutyCycle(LPC_I2C_T *pI2C, uint16_t sclH, uint16_t sclL)
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{
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pI2C->SCLH = (uint32_t) sclH;
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pI2C->SCLL = (uint32_t) sclL;
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}
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/**
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* @brief Set up bus speed for LPC_I2C controller
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* @param pI2C : Pointer to selected I2C peripheral
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* @param busSpeed : I2C bus clock rate
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* @return Nothing
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* @note Per I2C specification the busSpeed should be
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* @li 100000 for Standard mode
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* @li 400000 for Fast mode
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* @li 1000000 for Fast mode plus
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* IOCON registers corresponding to I2C pads should be updated
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* according to the bus mode.
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*/
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void Chip_I2CM_SetBusSpeed(LPC_I2C_T *pI2C, uint32_t busSpeed);
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/**
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* @brief Transmit START or Repeat-START signal on I2C bus
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* @param pI2C : Pointer to selected I2C peripheral
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* @return Nothing
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* @note This function sets the controller to transmit START condition when
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* the bus becomes free.
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*/
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static INLINE void Chip_I2CM_SendStart(LPC_I2C_T *pI2C)
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{
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pI2C->CONSET = I2C_CON_I2EN | I2C_CON_STA;
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}
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/**
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* @brief Reset I2C controller state
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* @param pI2C : Pointer to selected I2C peripheral
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* @return Nothing
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* @note This function clears all control/status flags.
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*/
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static INLINE void Chip_I2CM_ResetControl(LPC_I2C_T *pI2C)
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{
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/* Reset STA, STO, SI */
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pI2C->CONCLR = I2C_CON_SI | I2C_CON_STO | I2C_CON_STA | I2C_CON_AA;
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}
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/**
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* @brief Transmit a single data byte through the I2C peripheral
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* @param pI2C : Pointer to selected I2C peripheral
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* @param data : Byte to transmit
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* @return Nothing
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* @note This function attempts to place a byte into the UART transmit
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* FIFO or transmit hold register regard regardless of UART state
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*
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*/
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static INLINE void Chip_I2CM_WriteByte(LPC_I2C_T *pI2C, uint8_t data)
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{
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pI2C->DAT = (uint32_t) data;
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}
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/**
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* @brief Read a single byte data from the I2C peripheral
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* @param pI2C : Pointer to selected I2C peripheral
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* @return A single byte of data read
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* @note This function reads a byte from the I2C receive hold register
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* regardless of I2C state. The I2C status should be read first prior
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* to using this function.
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*/
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static INLINE uint8_t Chip_I2CM_ReadByte(LPC_I2C_T *pI2C)
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{
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return (uint8_t) (pI2C->DAT & I2C_I2DAT_BITMASK);
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}
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/**
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* @brief Generate NACK after receiving next byte
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* @param pI2C : Pointer to selected I2C peripheral
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* @return Nothing
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* @note This function sets the controller to NACK after receiving next
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* byte from slave transmitter. Used before receiving last byte.
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*/
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static INLINE void Chip_I2CM_NackNextByte(LPC_I2C_T *pI2C)
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{
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pI2C->CONCLR = I2C_CON_AA;
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}
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/**
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* @brief Transmit STOP signal on I2C bus
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* @param pI2C : Pointer to selected I2C peripheral
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* @return Nothing
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* @note This function sets the controller to transmit STOP condition.
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*/
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static INLINE void Chip_I2CM_SendStop(LPC_I2C_T *pI2C)
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{
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pI2C->CONSET = I2C_CON_STO;
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}
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/**
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* @brief Force start I2C transmit
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* @param pI2C : Pointer to selected I2C peripheral
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* @return Nothing
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* @note This function force I2C state machine to start transmitting.
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* If an uncontrolled source generates a superfluous START or masks
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* a STOP condition, then the I2C-bus stays busy indefinitely. If
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* the STA flag is set and bus access is not obtained within a
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* reasonable amount of time, then a forced access to the I2C-bus is
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* possible. This is achieved by setting the STO flag while the STA
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* flag is still set. No STOP condition is transmitted.
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*/
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static INLINE void Chip_I2CM_ForceStart(LPC_I2C_T *pI2C)
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{
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/* check if we are pending on start */
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if (pI2C->CONSET & I2C_CON_STA) {
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pI2C->CONSET = I2C_CON_STO;
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}
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else {
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Chip_I2CM_SendStart(pI2C);
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}
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}
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/**
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* @brief Transmit STOP+START signal on I2C bus
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* @param pI2C : Pointer to selected I2C peripheral
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* @return Nothing
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* @note This function sets the controller to transmit STOP condition
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* followed by a START condition.
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*/
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static INLINE void Chip_I2CM_SendStartAfterStop(LPC_I2C_T *pI2C)
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{
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pI2C->CONSET = I2C_CON_STO | I2C_CON_STA;
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}
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/**
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* @brief Check if I2C controller state changed
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* @param pI2C : Pointer to selected I2C peripheral
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* @return Returns 0 if state didn't change
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* @note
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*/
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static INLINE uint32_t Chip_I2CM_StateChanged(LPC_I2C_T *pI2C)
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{
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return pI2C->CONSET & I2C_CON_SI;
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}
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/**
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* @brief Clear state change interrupt flag
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* @param pI2C : Pointer to selected I2C peripheral
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* @return Nothing
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* @note
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*/
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static INLINE void Chip_I2CM_ClearSI(LPC_I2C_T *pI2C)
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{
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pI2C->CONCLR = I2C_CON_SI | I2C_CON_STO | I2C_CON_STA;
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}
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/**
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* @brief Check if I2C bus is free per our controller
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* @param pI2C : Pointer to selected I2C peripheral
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* @return Returns 0 if busy else a non-zero value.
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* @note I2C controller clears STO bit when it sees STOP
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* condition after a START condition on the bus.
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*/
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static INLINE uint32_t Chip_I2CM_BusFree(LPC_I2C_T *pI2C)
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{
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return !(pI2C->CONSET & I2C_CON_STO);
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}
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/**
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* @brief Get current state of the I2C controller
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* @param pI2C : Pointer to selected I2C peripheral
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* @return Returns 0 if busy else a non-zero value.
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* @note I2C controller clears STO bit when it sees STOP
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* condition after a START condition on the bus.
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*/
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static INLINE uint32_t Chip_I2CM_GetCurState(LPC_I2C_T *pI2C)
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{
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return pI2C->STAT & I2C_STAT_CODE_BITMASK;
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}
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/**
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* @brief Disable I2C interface
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* @param pI2C : Pointer to selected I2C peripheral
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* @return Nothing
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* @note
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*/
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static INLINE void Chip_I2CM_Disable(LPC_I2C_T *pI2C)
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{
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pI2C->CONCLR = I2C_CON_I2EN;
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}
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/**
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* @brief Transfer state change handler handler
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* @param pI2C : Pointer to selected I2C peripheral
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* @param xfer : Pointer to a I2CM_XFER_T structure see notes below
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* @return Returns non-zero value on completion of transfer. The @a status
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* member of @a xfer structure contains the current status of the
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* transfer at the end of the call.
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* @note
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* The parameter @a xfer should be same as the one passed to Chip_I2CM_Xfer()
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* routine.
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*/
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uint32_t Chip_I2CM_XferHandler(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer);
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/**
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* @brief Transmit and Receive data in master mode
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* @param pI2C : Pointer to selected I2C peripheral
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* @param xfer : Pointer to a I2CM_XFER_T structure see notes below
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* @return Nothing.
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* @note
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* The parameter @a xfer should have its member @a slaveAddr initialized
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* to the 7-Bit slave address to which the master will do the xfer, Bit0
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* to bit6 should have the address and Bit8 is ignored. During the transfer
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* no code (like event handler) must change the content of the memory
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* pointed to by @a xfer. The member of @a xfer, @a txBuff and @a txSz be
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* initialized to the memory from which the I2C must pick the data to be
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* transfered to slave and the number of bytes to send respectively, similarly
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* @a rxBuff and @a rxSz must have pointer to memroy where data received
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* from slave be stored and the number of data to get from slave respectilvely.
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* Following types of transfers are possible:
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* - Write-only transfer: When @a rxSz member of @a xfer is set to 0.
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*
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* S Addr Wr [A] txBuff0 [A] txBuff1 [A] ... txBuffN [A] P
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*
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* - If I2CM_XFER_OPTION_IGNORE_NACK is set in @a options memeber
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*
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* S Addr Wr [A] txBuff0 [A or NA] ... txBuffN [A or NA] P
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*
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* - Read-only transfer: When @a txSz member of @a xfer is set to 0.
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*
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* S Addr Rd [A] [rxBuff0] A [rxBuff1] A ... [rxBuffN] NA P
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*
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* - If I2CM_XFER_OPTION_LAST_RX_ACK is set in @a options memeber
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*
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* S Addr Rd [A] [rxBuff0] A [rxBuff1] A ... [rxBuffN] A P
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*
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* - Read-Write transfer: When @a rxSz and @ txSz members of @a xfer are non-zero.
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*
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* S Addr Wr [A] txBuff0 [A] txBuff1 [A] ... txBuffN [A]
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* S Addr Rd [A] [rxBuff0] A [rxBuff1] A ... [rxBuffN] NA P
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*
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*/
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void Chip_I2CM_Xfer(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer);
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/**
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* @brief Transmit and Receive data in master mode
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* @param pI2C : Pointer to selected I2C peripheral
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* @param xfer : Pointer to a I2CM_XFER_T structure see notes below
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* @return Returns non-zero value on succesful completion of transfer.
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* @note
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* This function operates same as Chip_I2CM_Xfer(), but is a blocking call.
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*/
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uint32_t Chip_I2CM_XferBlocking(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer);
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/**
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* @brief Write given buffer of data to I2C interface
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* @param pI2C : Pointer to selected I2C peripheral
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* @param buff : Pointer to buffer to be transmitted
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* @param len : Length of the buffer
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* @return Returns number of bytes written.
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* @note This function is a blocking call. The function generates
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* START/repeat-START condition on bus and starts transmitting
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* data untill transfer finishes or a NACK is received. No
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* STOP condition is transmitted on the bus.
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*
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* S Data0 [A] Data1 [A] ... DataN [A]
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*/
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uint32_t Chip_I2CM_Write(LPC_I2C_T *pI2C, const uint8_t *buff, uint32_t len);
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/**
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* @brief Read data from I2C slave to given buffer
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* @param pI2C : Pointer to selected I2C peripheral
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* @param buff : Pointer to buffer for data received from I2C slave
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* @param len : Length of the buffer
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* @return Returns number of bytes read.
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* @note This function is a blocking call. The function generates
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* START/repeat-START condition on bus and starts reading
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* data untill requested number of bytes are read. No
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* STOP condition is transmitted on the bus.
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*
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* S [Data0] A [Data1] A ... [DataN] A
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*/
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uint32_t Chip_I2CM_Read(LPC_I2C_T *pI2C, uint8_t *buff, uint32_t len);
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __I2C_11U6X_H_ */
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