206 lines
6.7 KiB
C
206 lines
6.7 KiB
C
/*
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* @brief LPC11U6x GPIO group driver
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2013
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __GPIOGROUP_11U6X_H_
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#define __GPIOGROUP_11U6X_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @defgroup GPIOGP_11U6X CHIP: LPC11u6x GPIO group driver
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* @ingroup CHIP_11U6X_Drivers
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* @{
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*/
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/**
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* @brief GPIO grouped interrupt register block structure
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*/
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typedef struct { /*!< GPIO_GROUP_INTn Structure */
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__IO uint32_t CTRL; /*!< GPIO grouped interrupt control register */
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__I uint32_t RESERVED0[7];
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__IO uint32_t PORT_POL[8]; /*!< GPIO grouped interrupt port polarity register */
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__IO uint32_t PORT_ENA[8]; /*!< GPIO grouped interrupt port m enable register */
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uint32_t RESERVED1[4072];
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} LPC_GPIOGROUPINT_T;
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/**
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* LPC11u6x GPIO group bit definitions
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*/
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#define GPIOGR_INT (1 << 0) /*!< GPIO interrupt pending/clear bit */
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#define GPIOGR_COMB (1 << 1) /*!< GPIO interrupt OR(0)/AND(1) mode bit */
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#define GPIOGR_TRIG (1 << 2) /*!< GPIO interrupt edge(0)/level(1) mode bit */
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/**
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* @brief Clear interrupt pending status for the selected group
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* @param pGPIOGPINT : Pointer to GPIO group register block
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* @param group : GPIO group number
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* @return None
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*/
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STATIC INLINE void Chip_GPIOGP_ClearIntStatus(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group)
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{
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uint32_t temp;
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temp = pGPIOGPINT[group].CTRL;
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pGPIOGPINT[group].CTRL = temp | GPIOGR_INT;
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}
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/**
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* @brief Returns current GPIO group inetrrupt pending status
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* @param pGPIOGPINT : Pointer to GPIO group register block
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* @param group : GPIO group number
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* @return true if the group interrupt is pending, otherwise false.
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*/
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STATIC INLINE bool Chip_GPIOGP_GetIntStatus(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group)
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{
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return (bool) ((pGPIOGPINT[group].CTRL & GPIOGR_INT) != 0);
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}
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/**
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* @brief Selected GPIO group functionality for trigger on any pin in group (OR mode)
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* @param pGPIOGPINT : Pointer to GPIO group register block
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* @param group : GPIO group number
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* @return None
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*/
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STATIC INLINE void Chip_GPIOGP_SelectOrMode(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group)
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{
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pGPIOGPINT[group].CTRL &= ~GPIOGR_COMB;
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}
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/**
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* @brief Selected GPIO group functionality for trigger on all matching pins in group (AND mode)
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* @param pGPIOGPINT : Pointer to GPIO group register block
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* @param group : GPIO group number
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* @return None
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*/
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STATIC INLINE void Chip_GPIOGP_SelectAndMode(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group)
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{
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pGPIOGPINT[group].CTRL |= GPIOGR_COMB;
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}
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/**
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* @brief Selected GPIO group functionality edge trigger mode
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* @param pGPIOGPINT : Pointer to GPIO group register block
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* @param group : GPIO group number
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* @return None
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*/
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STATIC INLINE void Chip_GPIOGP_SelectEdgeMode(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group)
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{
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pGPIOGPINT[group].CTRL &= ~GPIOGR_TRIG;
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}
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/**
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* @brief Selected GPIO group functionality level trigger mode
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* @param pGPIOGPINT : Pointer to GPIO group register block
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* @param group : GPIO group number
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* @return None
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*/
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STATIC INLINE void Chip_GPIOGP_SelectLevelMode(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group)
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{
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pGPIOGPINT[group].CTRL |= GPIOGR_TRIG;
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}
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/**
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* @brief Set selected pins for the group and port to low level trigger
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* @param pGPIOGPINT : Pointer to GPIO group register block
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* @param group : GPIO group number
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* @param port : GPIO port number
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* @param pinMask : Or'ed value of pins to select for low level (bit 0 = pin 0, 1 = pin1, etc.)
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* @return None
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*/
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STATIC INLINE void Chip_GPIOGP_SelectLowLevel(LPC_GPIOGROUPINT_T *pGPIOGPINT,
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uint8_t group,
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uint8_t port,
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uint32_t pinMask)
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{
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pGPIOGPINT[group].PORT_POL[port] &= ~pinMask;
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}
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/**
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* @brief Set selected pins for the group and port to high level trigger
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* @param pGPIOGPINT : Pointer to GPIO group register block
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* @param group : GPIO group number
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* @param port : GPIO port number
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* @param pinMask : Or'ed value of pins to select for high level (bit 0 = pin 0, 1 = pin1, etc.)
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* @return None
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*/
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STATIC INLINE void Chip_GPIOGP_SelectHighLevel(LPC_GPIOGROUPINT_T *pGPIOGPINT,
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uint8_t group,
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uint8_t port,
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uint32_t pinMask)
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{
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pGPIOGPINT[group].PORT_POL[port] |= pinMask;
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}
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/**
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* @brief Disabled selected pins for the group interrupt
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* @param pGPIOGPINT : Pointer to GPIO group register block
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* @param group : GPIO group number
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* @param port : GPIO port number
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* @param pinMask : Or'ed value of pins to disable interrupt for (bit 0 = pin 0, 1 = pin1, etc.)
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* @return None
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* @note Disabled pins do not contribute to the group interrupt.
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*/
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STATIC INLINE void Chip_GPIOGP_DisableGroupPins(LPC_GPIOGROUPINT_T *pGPIOGPINT,
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uint8_t group,
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uint8_t port,
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uint32_t pinMask)
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{
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pGPIOGPINT[group].PORT_ENA[port] &= ~pinMask;
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}
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/**
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* @brief Enable selected pins for the group interrupt
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* @param pGPIOGPINT : Pointer to GPIO group register block
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* @param group : GPIO group number
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* @param port : GPIO port number
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* @param pinMask : Or'ed value of pins to enable interrupt for (bit 0 = pin 0, 1 = pin1, etc.)
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* @return None
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* @note Enabled pins contribute to the group interrupt.
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*/
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STATIC INLINE void Chip_GPIOGP_EnableGroupPins(LPC_GPIOGROUPINT_T *pGPIOGPINT,
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uint8_t group,
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uint8_t port,
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uint32_t pinMask)
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{
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pGPIOGPINT[group].PORT_ENA[port] |= pinMask;
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}
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __GPIOGROUP_11U6X_H_ */
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