154 lines
6.9 KiB
C
154 lines
6.9 KiB
C
/*
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* @brief Basic CMSIS include file for LPC11U6X
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2013
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __CMSIS_11U6X_H_
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#define __CMSIS_11U6X_H_
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#include "lpc_types.h"
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#include "sys_config.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @defgroup CMSIS_11U6X CHIP: LPC11U6X CMSIS include file
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* @ingroup CHIP_11U6X_CMSIS_Drivers
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* @{
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*/
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#if defined(__ARMCC_VERSION)
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// Kill warning "#pragma push with no matching #pragma pop"
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#pragma diag_suppress 2525
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#pragma push
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#pragma anon_unions
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#elif defined(__CWCC__)
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#pragma push
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#pragma cpp_extensions on
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#elif defined(__GNUC__)
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/* anonymous unions are enabled by default */
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#elif defined(__IAR_SYSTEMS_ICC__)
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// #pragma push // FIXME not usable for IAR
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#pragma language=extended
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#else
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#error Not supported compiler type
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#endif
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/*
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* ==========================================================================
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* ---------- Interrupt Number Definition -----------------------------------
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* ==========================================================================
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*/
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#if !defined(CHIP_LPC11U6X)
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#error Incorrect or missing device variant (CHIP_LPC11U6X)
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#endif
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/** @defgroup CMSIS_11U6X_IRQ CHIP_LPC11U6X: CHIP_LPC11U6X peripheral interrupt numbers
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* @{
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*/
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typedef enum {
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NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
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HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
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SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
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PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
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SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
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PIN_INT0_IRQn = 0, /*!< Pin Interrupt 0 */
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PIN_INT1_IRQn = 1, /*!< Pin Interrupt 1 */
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PIN_INT2_IRQn = 2, /*!< Pin Interrupt 2 */
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PIN_INT3_IRQn = 3, /*!< Pin Interrupt 3 */
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PIN_INT4_IRQn = 4, /*!< Pin Interrupt 4 */
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PIN_INT5_IRQn = 5, /*!< Pin Interrupt 5 */
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PIN_INT6_IRQn = 6, /*!< Pin Interrupt 6 */
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PIN_INT7_IRQn = 7, /*!< Pin Interrupt 7 */
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GINT0_IRQn = 8, /*!< GPIO interrupt status of port 0 */
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GINT1_IRQn = 9, /*!< GPIO interrupt status of port 1 */
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I2C1_IRQn = 10, /*!< I2C1 Interrupt */
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USART1_4_IRQn = 11, /*!< Combined USART1 and USART4 interrupts */
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USART2_3_IRQn = 12, /*!< Combined USART2 and USART3 interrupts */
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SCT0_1_IRQn = 13, /*!< Combined SCT0 and SCT1 interrupts */
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SSP1_IRQn = 14, /*!< SSP1 Interrupt */
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I2C0_IRQn = 15, /*!< I2C0 Interrupt */
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TIMER_16_0_IRQn = 16, /*!< 16-bit Timer0 Interrupt */
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TIMER_16_1_IRQn = 17, /*!< 16-bit Timer1 Interrupt */
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TIMER_32_0_IRQn = 18, /*!< 32-bit Timer0 Interrupt */
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TIMER_32_1_IRQn = 19, /*!< 32-bit Timer1 Interrupt */
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SSP0_IRQn = 20, /*!< SSP0 Interrupt */
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USART0_IRQn = 21, /*!< USART0 interrupt */
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USB0_IRQn = 22, /*!< USB IRQ interrupt */
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USB0_FIQ_IRQn = 23, /*!< USB FIQ interrupt */
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ADC_A_IRQn = 24, /*!< ADC_A Converter Interrupt */
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RTC_IRQn = 25, /*!< RTC Interrupt */
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BOD_WDT_IRQn = 26, /*!< Shared Brown Out Detect(BOD) and WDT Interrupts */
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FMC_IRQn = 27, /*!< FLASH Interrupt */
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DMA_IRQn = 28, /*!< DMA Interrupt */
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ADC_B_IRQn = 29, /*!< ADC_B Interrupt */
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USB_WAKEUP_IRQn = 30, /*!< USB wake-up interrupt Interrupt */
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RESERVED31_IRQn = 31,
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} IRQn_Type;
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/**
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* @}
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*/
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/*
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* ==========================================================================
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* ----------- Processor and Core Peripheral Section ------------------------
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* ==========================================================================
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*/
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/** @defgroup CMSIS_11U6X_COMMON CHIP: LPC11U6X Cortex CMSIS definitions
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* @{
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*/
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/* Configuration of the Cortex-M0+ Processor and Core Peripherals */
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#define __CM0_REV 0x0000 /*!< Cortex-M0 Core Revision */
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#define __MPU_PRESENT 0 /*!< MPU present or not */
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#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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/**
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* @}
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*/
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#include "core_cm0plus.h" /*!< Cortex-M0+ processor and core peripherals */
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __CMSIS_11U6X_H_ */
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