4103cc374f
temporarily implement hidd_init using dcd from lpc17xx add more test for dcd lp176x implement dcd_endpoint_configure
209 lines
7.5 KiB
C
209 lines
7.5 KiB
C
/**************************************************************************/
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/*!
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@file dcd_lpc175x_6x.h
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@author hathach (tinyusb.org)
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@section LICENSE
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Software License Agreement (BSD License)
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Copyright (c) 2013, hathach (tinyusb.org)
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the copyright holders nor the
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names of its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
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EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
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DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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This file is part of the tinyusb stack.
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*/
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/**************************************************************************/
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/** \ingroup TBD
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* \defgroup TBD
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* \brief TBD
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*
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* @{
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*/
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#ifndef _TUSB_DCD_LPC175X_6X_H_
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#define _TUSB_DCD_LPC175X_6X_H_
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#include "common/common.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef struct
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{
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//------------- Word 0 -------------//
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uint32_t next;
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//------------- Word 1 -------------//
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uint16_t mode : 2; // either 00 normal or 01 ATLE(auto length extraction)
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uint16_t is_next_valid : 1;
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uint16_t : 1;
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uint16_t is_isochronous : 1; // is an iso endpoint
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uint16_t max_packet_size : 11;
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volatile uint16_t buffer_length;
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//------------- Word 2 -------------//
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volatile uint32_t buffer_start_addr;
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//------------- Word 3 -------------//
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volatile uint16_t is_retired : 1; // initialized to zero
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volatile uint16_t status : 4;
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volatile uint16_t iso_last_packet_valid : 1;
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volatile uint16_t atle_is_lsb_extracted : 1; // used in ATLE mode
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volatile uint16_t atle_is_msb_extracted : 1; // used in ATLE mode
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volatile uint16_t atle_message_length_position : 6; // used in ATLE mode
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uint16_t : 2;
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volatile uint16_t present_count; // The number of bytes transferred by the DMA engine. The DMA engine updates this field after completing each packet transfer.
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//------------- Word 4 -------------//
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// uint32_t iso_packet_size_addr; // iso only, can be omitted for non-iso
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} ATTR_ALIGNED(4) dcd_dma_descriptor_t;
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#define DCD_MAX_DD 32 // TODO scale with configure
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//typedef struct {
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// dcd_dma_descriptor_t dd[DCD_MAX_DD];
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//
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//}dcd_data_t;
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//--------------------------------------------------------------------+
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// Register Interface
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//--------------------------------------------------------------------+
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//------------- USB Interrupt USBIntSt -------------//
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//enum {
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// DCD_USB_REQ_LOW_PRIO_MASK = BIT_(0),
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// DCD_USB_REQ_HIGH_PRIO_MASK = BIT_(1),
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// DCD_USB_REQ_DMA_MASK = BIT_(2),
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// DCD_USB_REQ_NEED_CLOCK_MASK = BIT_(8),
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// DCD_USB_REQ_ENABLE_MASK = BIT_(31)
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//};
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//------------- Device Interrupt USBDevInt -------------//
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enum {
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DEV_INT_FRAME_MASK = BIT_(0),
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DEV_INT_ENDPOINT_FAST_MASK = BIT_(1),
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DEV_INT_ENDPOINT_SLOW_MASK = BIT_(2),
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DEV_INT_DEVICE_STATUS_MASK = BIT_(3),
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DEV_INT_COMMAND_CODE_EMPTY_MASK = BIT_(4),
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DEV_INT_COMMAND_DATA_FULL_MASK = BIT_(5),
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DEV_INT_RX_ENDPOINT_PACKET_MASK = BIT_(6),
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DEV_INT_TX_ENDPOINT_PACKET_MASK = BIT_(7),
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DEV_INT_ENDPOINT_REALIZED_MASK = BIT_(8),
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DEV_INT_ERROR_MASK = BIT_(9),
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DEV_INT_ALL_MASK = DEV_INT_FRAME_MASK | DEV_INT_ENDPOINT_FAST_MASK | DEV_INT_ENDPOINT_SLOW_MASK |
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DEV_INT_DEVICE_STATUS_MASK | DEV_INT_COMMAND_CODE_EMPTY_MASK | DEV_INT_COMMAND_DATA_FULL_MASK |
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DEV_INT_RX_ENDPOINT_PACKET_MASK | DEV_INT_TX_ENDPOINT_PACKET_MASK | DEV_INT_ENDPOINT_REALIZED_MASK |
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DEV_INT_ERROR_MASK
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};
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//------------- DMA Interrupt USBDMAInt-------------//
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enum {
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DMA_INT_END_OF_XFER_MASK = BIT_(0),
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DMA_INT_NEW_DD_REQUEST_MASK = BIT_(1),
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DMA_INT_ERROR_MASK = BIT_(2)
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};
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//------------- USBCtrl -------------//
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enum {
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SLAVE_CONTROL_READ_ENABLE_MASK = BIT_(0),
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SLAVE_CONTROL_WRITE_ENABLE_MASK = BIT_(1),
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SLAVE_CONTROL_READ_ENABLE_POS = 2
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};
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//------------- USBRxPLen -------------//
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enum {
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SLAVE_RXPLEN_PACKET_LENGTH_MASK = (BIT_(10)-1),
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SLAVE_RXPLEN_DATA_VALID_MASK = BIT_(10),
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SLAVE_RXPLEN_PACKET_READY_MASK = BIT_(11),
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};
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//------------- SIE Command Code -------------//
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enum {
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SIE_CMDPHASE_WRITE = 1,
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SIE_CMDPHASE_READ = 2,
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SIE_CMDPHASE_COMMAND = 5
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};
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enum {
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// device commands
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SIE_CMDCODE_SET_ADDRESS = 0xd0,
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SIE_CMDCODE_CONFIGURE_DEVICE = 0xd8,
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SIE_CMDCODE_SET_MODE = 0xf3,
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SIE_CMDCODE_READ_FRAME_NUMBER = 0xf5,
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SIE_CMDCODE_READ_TEST_REGISTER = 0xfd,
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SIE_CMDCODE_DEVICE_STATUS = 0xfe,
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SIE_CMDCODE_GET_ERROR = 0xff,
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SIE_CMDCODE_READ_ERROR_STATUS = 0xfb,
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// endpoint commands
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SIE_CMDCODE_ENDPOINT_SELECT = 0x00, // + endpoint index
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SIE_CMDCODE_ENDPOINT_SELECT_CLEAR_INTERRUPT = 0x40, // + endpoint index, should use USBEpIntClr instead
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SIE_CMDCODE_ENDPOINT_SET_STATUS = 0x40, // + endpoint index
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SIE_CMDCODE_BUFFER_CLEAR = 0xf2,
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SIE_CMDCODE_BUFFER_VALIDATE = 0xfa
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};
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//------------- SIE Device Status (get/set from SIE_CMDCODE_DEVICE_STATUS) -------------//
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enum {
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SIE_DEV_STATUS_CONNECT_MASK = BIT_(0),
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SIE_DEV_STATUS_CONNECT_CHANGE_MASK = BIT_(1),
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SIE_DEV_STATUS_SUSPEND_MASK = BIT_(2),
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SIE_DEV_STATUS_SUSPEND_CHANGE_MASK = BIT_(3),
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SIE_DEV_STATUS_RESET_MASK = BIT_(4)
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};
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//------------- SIE Endpoint Status -------------//
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enum {
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SIE_ENDPOINT_STATUS_FULL_EMPTY_MASK = BIT_(0), // 0: empty, 1 full. IN endpoint checks empty, OUT endpoint check full
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SIE_ENDPOINT_STATUS_STALL_MASK = BIT_(1),
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SIE_ENDPOINT_STATUS_SETUP_RECEIVED_MASK = BIT_(2), // clear by SIE_CMDCODE_ENDPOINT_SELECT_CLEAR_INTERRUPT
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SIE_ENDPOINT_STATUS_PACKET_OVERWRITTEN_MASK = BIT_(3), // previous packet is overwritten by a SETUP packet
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SIE_ENDPOINT_STATUS_NAK_MASK = BIT_(4), // last packet response is NAK (auto clear by an ACK)
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SIE_ENDPOINT_STATUS_BUFFER1_FULL_MASK = BIT_(5),
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SIE_ENDPOINT_STATUS_BUFFER2_FULL_MASK = BIT_(6)
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};
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//------------- DMA Descriptor Status -------------//
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enum {
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DD_STATUS_NOT_SERVICED = 0,
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DD_STATUS_BEING_SERVICED,
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DD_STATUS_NORMAL,
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DD_STATUS_DATA_UNDERUN, // short packet
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DD_STATUS_DATA_OVERRUN,
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DD_STATUS_SYSTEM_ERROR
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /* _TUSB_DCD_LPC175X_6X_H_ */
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/** @} */
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