71 lines
		
	
	
		
			1.6 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			71 lines
		
	
	
		
			1.6 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| #ifndef __IRQ_H
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| #define __IRQ_H
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| 
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| #ifdef __cplusplus
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| extern "C" {
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| #endif
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| 
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| 
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| #define CSR_MSTATUS_MIE 0x8
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| 
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| #define CSR_IRQ_MASK 0xBC0
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| #define CSR_IRQ_PENDING 0xFC0
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| 
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| #define CSR_DCACHE_INFO 0xCC0
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| 
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| #define csrr(reg) ({ unsigned long __tmp; \
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|   asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
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|   __tmp; })
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| 
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| #define csrw(reg, val) ({ \
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|   if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
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| 	asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
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|   else \
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| 	asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
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| 
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| #define csrs(reg, bit) ({ \
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|   if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
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| 	asm volatile ("csrrs x0, " #reg ", %0" :: "i"(bit)); \
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|   else \
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| 	asm volatile ("csrrs x0, " #reg ", %0" :: "r"(bit)); })
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| 
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| #define csrc(reg, bit) ({ \
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|   if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
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| 	asm volatile ("csrrc x0, " #reg ", %0" :: "i"(bit)); \
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|   else \
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| 	asm volatile ("csrrc x0, " #reg ", %0" :: "r"(bit)); })
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| 
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| static inline unsigned int irq_getie(void)
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| {
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| 	return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0;
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| }
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| 
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| static inline void irq_setie(unsigned int ie)
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| {
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| 	if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE);
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| }
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| 
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| static inline unsigned int irq_getmask(void)
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| {
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| 	unsigned int mask;
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| 	asm volatile ("csrr %0, %1" : "=r"(mask) : "i"(CSR_IRQ_MASK));
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| 	return mask;
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| }
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| 
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| static inline void irq_setmask(unsigned int mask)
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| {
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| 	asm volatile ("csrw %0, %1" :: "i"(CSR_IRQ_MASK), "r"(mask));
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| }
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| 
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| static inline unsigned int irq_pending(void)
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| {
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| 	unsigned int pending;
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| 	asm volatile ("csrr %0, %1" : "=r"(pending) : "i"(CSR_IRQ_PENDING));
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| 	return pending;
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| }
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| 
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| #ifdef __cplusplus
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| }
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| #endif
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| 
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| #endif /* __IRQ_H */ | 
