572 lines
22 KiB
C
572 lines
22 KiB
C
/**********************************************************************
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* $Id$ lpc43xx_gpdma.c 2011-06-02
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*//**
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* @file lpc43xx_gpdma.c
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* @brief Contains all functions support for GPDMA firmware library
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* on lpc43xx
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* @version 1.0
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* @date 02. June. 2011
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* @author NXP MCU SW Application Team
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*
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* Copyright(C) 2011, NXP Semiconductor
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* All rights reserved.
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*
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***********************************************************************
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* products. This software is supplied "AS IS" without any warranties.
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* NXP Semiconductors assumes no responsibility or liability for the
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* use of the software, conveys no license or title under any patent,
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* copyright, or mask work right to the product. NXP Semiconductors
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* reserves the right to make changes in the software without
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* notification. NXP Semiconductors also make no representation or
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* warranty that such application will be suitable for the specified
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* use without further testing or modification.
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors’
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* relevant copyright in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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**********************************************************************/
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/* Peripheral group ----------------------------------------------------------- */
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/** @addtogroup GPDMA
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* @{
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*/
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/* Includes ------------------------------------------------------------------- */
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#include "lpc43xx_gpdma.h"
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//#include "lpc43xx_cgu.h"
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/* If this source file built with example, the lpc43xx FW library configuration
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* file in each example directory ("lpc43xx_libcfg.h") must be included,
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* otherwise the default FW library configuration file must be included instead
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*/
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#ifdef __BUILD_WITH_EXAMPLE__
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#include "lpc43xx_libcfg.h"
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#else
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#include "lpc43xx_libcfg_default.h"
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#endif /* __BUILD_WITH_EXAMPLE__ */
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#ifdef _GPDMA
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/** GPDMA Mux definitions */
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#define DMAMUX_ADDRESS 0x4004311C
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/* Private Functions ----------------------------------------------------------- */
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/** @
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* @{
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*/
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uint8_t DMAMUX_Config(uint32_t gpdma_peripheral_connection_number);
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/**
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* @}
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*/
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/* Private Variables ---------------------------------------------------------- */
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/** @defgroup GPDMA_Private_Variables GPDMA Private Variables
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* @{
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*/
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/**
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* @brief Lookup Table of Connection Type matched with
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* Peripheral Data (FIFO) register base address
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*/
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#ifdef __ICCARM__
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volatile const void *GPDMA_LUTPerAddr[] = {
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NULL,
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(&LPC_TIMER0->MR), // MAT0.0
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(&LPC_USART0->/*RBTHDLR.*/THR), // UART0 Tx
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((uint32_t*)&LPC_TIMER0->MR + 1), // MAT0.1
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(&LPC_USART0->/*RBTHDLR.*/RBR), // UART0 Rx
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(&LPC_TIMER1->MR), // MAT1.0
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(&LPC_UART1->/*RBTHDLR.*/THR), // UART1 Tx
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((uint32_t*)&LPC_TIMER1->MR + 1), // MAT1.1
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(&LPC_UART1->/*RBTHDLR.*/RBR), // UART1 Rx
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(&LPC_TIMER2->MR), // MAT2.0
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(&LPC_USART2->/*RBTHDLR.*/THR), // UART2 Tx
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((uint32_t*)&LPC_TIMER2->MR + 1), // MAT2.1
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(&LPC_USART2->/*RBTHDLR.*/RBR), // UART2 Rx
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(&LPC_TIMER3->MR), // MAT3.0
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(&LPC_USART3->/*RBTHDLR.*/THR), // UART3 Tx
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0, // to be defined: SCT DMA request 0
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((uint32_t*)&LPC_TIMER3->MR + 1), // MAT3.1
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(&LPC_USART3->/*RBTHDLR.*/RBR), // UART3 Rx
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0, // to be defined: SCT DMA request 1
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(&LPC_SSP0->DR), // SSP0 Rx
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(&LPC_I2S0->TXFIFO), // I2S channel 0
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(&LPC_SSP0->DR), // SSP0 Tx
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(&LPC_I2S0->RXFIFO), // I2S channel 1
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(&LPC_SSP1->DR), // SSP1 Rx
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(&LPC_SSP1->DR), // SSP1 Tx
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(&LPC_ADC0->GDR), // ADC 0
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(&LPC_ADC1->GDR), // ADC 1
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(&LPC_DAC->CR) // DAC
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};
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#else
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const uint32_t GPDMA_LUTPerAddr[] = {
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((uint32_t)0), // Reserved
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((uint32_t)&LPC_TIMER0->MR[0]), // MAT0.0
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((uint32_t)&LPC_USART0->/*RBTHDLR.*/THR), // UART0 Tx
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((uint32_t)&LPC_TIMER0->MR[1]), // MAT0.1
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((uint32_t)&LPC_USART0->/*RBTHDLR.*/RBR), // UART0 Rx
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((uint32_t)&LPC_TIMER1->MR[0]), // MAT1.0
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((uint32_t)&LPC_UART1->/*RBTHDLR.*/THR), // UART1 Tx
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((uint32_t)&LPC_TIMER1->MR[1]), // MAT1.1
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((uint32_t)&LPC_UART1->/*RBTHDLR.*/RBR), // UART1 Rx
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((uint32_t)&LPC_TIMER2->MR[0]), // MAT2.0
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((uint32_t)&LPC_USART2->/*RBTHDLR.*/THR), // UART2 Tx
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((uint32_t)&LPC_TIMER2->MR[1]), // MAT2.1
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((uint32_t)&LPC_USART2->/*RBTHDLR.*/RBR), // UART2 Rx
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((uint32_t)&LPC_TIMER3->MR[0]), // MAT3.0
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((uint32_t)&LPC_USART3->/*RBTHDLR.*/THR), // UART3 Tx
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0, // to be defined: SCT DMA request 0
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((uint32_t)&LPC_TIMER3->MR[1]), // MAT3.1
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((uint32_t)&LPC_USART3->/*RBTHDLR.*/RBR), // UART3 Rx
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0, // to be defined: SCT DMA request 1
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((uint32_t)&LPC_SSP0->DR), // SSP0 Rx
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((uint32_t)&LPC_I2S0->TXFIFO), // I2S channel 0
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((uint32_t)&LPC_SSP0->DR), // SSP0 Tx
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((uint32_t)&LPC_I2S0->RXFIFO), // I2S channel 1
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((uint32_t)&LPC_SSP1->DR), // SSP1 Rx
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((uint32_t)&LPC_SSP1->DR), // SSP1 Tx
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((uint32_t)&LPC_ADC0->GDR), // ADC 0
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((uint32_t)&LPC_ADC1->GDR), // ADC 1
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((uint32_t)&LPC_DAC->CR) // DAC
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};
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#endif
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/**
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* @brief Lookup Table of GPDMA Channel Number matched with
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* GPDMA channel pointer
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*/
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const LPC_GPDMACH_TypeDef *pGPDMACh[8] = {
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LPC_GPDMACH0, // GPDMA Channel 0
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LPC_GPDMACH1, // GPDMA Channel 1
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LPC_GPDMACH2, // GPDMA Channel 2
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LPC_GPDMACH3, // GPDMA Channel 3
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LPC_GPDMACH4, // GPDMA Channel 4
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LPC_GPDMACH5, // GPDMA Channel 5
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LPC_GPDMACH6, // GPDMA Channel 6
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LPC_GPDMACH7, // GPDMA Channel 7
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};
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/**
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* @brief Optimized Peripheral Source and Destination burst size
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*/
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const uint8_t GPDMA_LUTPerBurst[] = {
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GPDMA_BSIZE_4,
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GPDMA_BSIZE_1, // MAT0.0
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GPDMA_BSIZE_1, // UART0 Tx
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GPDMA_BSIZE_1, // MAT0.1
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GPDMA_BSIZE_1, // UART0 Rx
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GPDMA_BSIZE_1, // MAT1.0
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GPDMA_BSIZE_1, // UART1 Tx
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GPDMA_BSIZE_1, // MAT1.1
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GPDMA_BSIZE_1, // UART1 Rx
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GPDMA_BSIZE_1, // MAT2.0
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GPDMA_BSIZE_1, // UART2 Tx
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GPDMA_BSIZE_1, // MAT2.1
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GPDMA_BSIZE_1, // UART2 Rx
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GPDMA_BSIZE_1, // MAT3.0
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GPDMA_BSIZE_1, // UART3 Tx
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0, // to be defined: SCT DMA request 0
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GPDMA_BSIZE_1, // MAT3.1
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GPDMA_BSIZE_1, // UART3 Rx
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0, // to be defined: SCT DMA request 1
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GPDMA_BSIZE_4, // SSP0 Rx
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GPDMA_BSIZE_32, // I2S channel 0
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GPDMA_BSIZE_4, // SSP0 Tx
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GPDMA_BSIZE_32, // I2S channel 1
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GPDMA_BSIZE_4, // SSP1 Rx
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GPDMA_BSIZE_4, // SSP1 Tx
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GPDMA_BSIZE_4, // ADC 0
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GPDMA_BSIZE_4, // ADC 1
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GPDMA_BSIZE_1, // DAC
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};
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/**
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* @brief Optimized Peripheral Source and Destination transfer width
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*/
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const uint8_t GPDMA_LUTPerWid[] = {
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GPDMA_WIDTH_WORD,
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GPDMA_WIDTH_WORD, // MAT0.0
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GPDMA_WIDTH_BYTE, // UART0 Tx
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GPDMA_WIDTH_WORD, // MAT0.1
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GPDMA_WIDTH_BYTE, // UART0 Rx
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GPDMA_WIDTH_WORD, // MAT1.0
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GPDMA_WIDTH_BYTE, // UART1 Tx
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GPDMA_WIDTH_WORD, // MAT1.1
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GPDMA_WIDTH_BYTE, // UART1 Rx
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GPDMA_WIDTH_WORD, // MAT2.0
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GPDMA_WIDTH_BYTE, // UART2 Tx
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GPDMA_WIDTH_WORD, // MAT2.1
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GPDMA_WIDTH_BYTE, // UART2 Rx
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GPDMA_WIDTH_WORD, // MAT3.0
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GPDMA_WIDTH_BYTE, // UART3 Tx
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0, // to be defined: SCT DMA request 0
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GPDMA_WIDTH_WORD, // MAT3.1
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GPDMA_WIDTH_BYTE, // UART3 Rx
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0, // to be defined: SCT DMA request 1
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GPDMA_WIDTH_BYTE, // SSP0 Rx
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GPDMA_WIDTH_WORD, // I2S channel 0
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GPDMA_WIDTH_BYTE, // SSP0 Tx
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GPDMA_WIDTH_WORD, // I2S channel 1
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GPDMA_WIDTH_BYTE, // SSP1 Rx
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GPDMA_WIDTH_BYTE, // SSP1 Tx
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GPDMA_WIDTH_WORD, // ADC 0
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GPDMA_WIDTH_WORD, // ADC 1
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GPDMA_WIDTH_WORD, // DAC
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};
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/**
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* @}
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*/
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/* Private Functions ----------------------------------------------------------- */
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/** @
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* @{
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*/
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/********************************************************************//**
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* @brief Control which set of peripherals is connected to the
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* DMA controller
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* @param[in] gpdma_peripheral_connection_number GPDMA peripheral
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* connection number, should be:
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* - GPDMA_CONN_RESERVED
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* - GPDMA_CONN_MAT0_0 :Timer 0, match channel 0
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* - GPDMA_CONN_MAT0_1 :Timer 0, match channel 1
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* - GPDMA_CONN_MAT1_0 :Timer 1, match channel 0
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* - GPDMA_CONN_MAT1_1 :Timer 1, match channel 1
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* - GPDMA_CONN_MAT2_0 :Timer 2, match channel 0
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* - GPDMA_CONN_MAT2_1 :Timer 2, match channel 1
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* - GPDMA_CONN_MAT3_0 :Timer 3, match channel 0
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* - GPDMA_CONN_MAT3_1 :Timer 3, match channel 1
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* - GPDMA_CONN_UART0_Tx :USART 0 transmit
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* - GPDMA_CONN_UART0_Rx :USART 0 receive
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* - GPDMA_CONN_UART1_Tx :USART 1 transmit
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* - GPDMA_CONN_UART1_Rx :USART 1 receive
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* - GPDMA_CONN_UART2_Tx :USART 2 transmit
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* - GPDMA_CONN_UART2_Rx :USART 2 receive
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* - GPDMA_CONN_UART3_Tx :USART 3 transmit
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* - GPDMA_CONN_UART3_Rx :USART 3 receive
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* - GPDMA_CONN_SCT_0 :SCT output 0
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* - GPDMA_CONN_SCT_1 :SCT output 1
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* - GPDMA_CONN_I2S_Channel_0 :I2S channel 0
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* - GPDMA_CONN_I2S_Channel_1 :I2S channel 1
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* - GPDMA_CONN_SSP0_Tx :SSP0 transmit
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* - GPDMA_CONN_SSP0_Rx :SSP0 receive
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* - GPDMA_CONN_SSP1_Tx :SSP1 transmit
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* - GPDMA_CONN_SSP1_Rx :SSP1 receive
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* - GPDMA_CONN_ADC_0 :ADC0
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* - GPDMA_CONN_ADC_1 :ADC1
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* - GPDMA_CONN_DAC :DAC
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* @return channel number, could be in range: 0..16
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*********************************************************************/
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uint8_t DMAMUX_Config(uint32_t gpdma_peripheral_connection_number)
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{
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uint32_t *dmamux_reg = (uint32_t*)DMAMUX_ADDRESS;
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uint8_t function, channel;
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switch(gpdma_peripheral_connection_number)
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{
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case GPDMA_CONN_RESERVED: function = 0; channel = 0; break;
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case GPDMA_CONN_MAT0_0: function = 0; channel = 1; break;
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case GPDMA_CONN_UART0_Tx: function = 1; channel = 1; break;
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case GPDMA_CONN_MAT0_1: function = 0; channel = 2; break;
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case GPDMA_CONN_UART0_Rx: function = 1; channel = 2; break;
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case GPDMA_CONN_MAT1_0: function = 0; channel = 3; break;
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case GPDMA_CONN_UART1_Tx: function = 1; channel = 3; break;
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case GPDMA_CONN_MAT1_1: function = 0; channel = 4; break;
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case GPDMA_CONN_UART1_Rx: function = 1; channel = 4; break;
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case GPDMA_CONN_MAT2_0: function = 0; channel = 5; break;
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case GPDMA_CONN_UART2_Tx: function = 1; channel = 5; break;
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case GPDMA_CONN_MAT2_1: function = 0; channel = 6; break;
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case GPDMA_CONN_UART2_Rx: function = 1; channel = 6; break;
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case GPDMA_CONN_MAT3_0: function = 0; channel = 7; break;
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case GPDMA_CONN_UART3_Tx: function = 1; channel = 7; break;
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case GPDMA_CONN_SCT_0: function = 2; channel = 7; break;
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case GPDMA_CONN_MAT3_1: function = 0; channel = 8; break;
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case GPDMA_CONN_UART3_Rx: function = 1; channel = 8; break;
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case GPDMA_CONN_SCT_1: function = 2; channel = 8; break;
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case GPDMA_CONN_SSP0_Rx: function = 0; channel = 9; break;
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case GPDMA_CONN_I2S_Channel_0:function = 1; channel = 9; break;
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case GPDMA_CONN_SSP0_Tx: function = 0; channel = 10; break;
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case GPDMA_CONN_I2S_Channel_1:function = 1; channel = 10; break;
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case GPDMA_CONN_SSP1_Rx: function = 0; channel = 11; break;
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case GPDMA_CONN_SSP1_Tx: function = 0; channel = 12; break;
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case GPDMA_CONN_ADC_0: function = 0; channel = 13; break;
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case GPDMA_CONN_ADC_1: function = 0; channel = 14; break;
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case GPDMA_CONN_DAC: function = 0; channel = 15; break;
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default: function = 3; channel = 15; break;
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}
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//Set select function to dmamux register
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*dmamux_reg &= ~(0x03<<(2*channel));
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*dmamux_reg |= (function<<(2*channel));
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return channel;
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}
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/**
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* @}
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*/
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/* Public Functions ----------------------------------------------------------- */
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/** @addtogroup GPDMA_Public_Functions
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* @{
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*/
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/********************************************************************//**
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* @brief Initialize GPDMA controller
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* @param[in] None
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* @return None
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*********************************************************************/
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void GPDMA_Init(void)
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{
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/* to be defined Enable GPDMA clock */
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// enabled default on reset
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// Reset all channel configuration register
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LPC_GPDMACH0->CConfig = 0;
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LPC_GPDMACH1->CConfig = 0;
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LPC_GPDMACH2->CConfig = 0;
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LPC_GPDMACH3->CConfig = 0;
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LPC_GPDMACH4->CConfig = 0;
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LPC_GPDMACH5->CConfig = 0;
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LPC_GPDMACH6->CConfig = 0;
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LPC_GPDMACH7->CConfig = 0;
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/* Clear all DMA interrupt and error flag */
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LPC_GPDMA->INTTCCLEAR = 0xFF;
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LPC_GPDMA->INTERRCLR = 0xFF;
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}
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/********************************************************************//**
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* @brief Setup GPDMA channel peripheral according to the specified
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* parameters in the GPDMAChannelConfig.
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* @param[in] GPDMAChannelConfig Pointer to a GPDMA_CH_CFG_Type structure
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* that contains the configuration information for the specified
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* GPDMA channel peripheral.
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* @return Setup status, could be:
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* - ERROR :if selected channel is enabled before
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* - SUCCESS :if channel is configured successfully
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*********************************************************************/
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Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig)
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{
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LPC_GPDMACH_TypeDef *pDMAch;
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uint8_t SrcPeripheral=0, DestPeripheral=0;
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if (LPC_GPDMA->ENBLDCHNS & (GPDMA_DMACEnbldChns_Ch(GPDMAChannelConfig->ChannelNum))) {
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// This channel is enabled, return ERROR, need to release this channel first
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return ERROR;
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}
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// Get Channel pointer
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pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[GPDMAChannelConfig->ChannelNum];
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// Reset the Interrupt status
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LPC_GPDMA->INTTCCLEAR = GPDMA_DMACIntTCClear_Ch(GPDMAChannelConfig->ChannelNum);
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LPC_GPDMA->INTERRCLR = GPDMA_DMACIntErrClr_Ch(GPDMAChannelConfig->ChannelNum);
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// Clear DMA configure
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pDMAch->CControl = 0x00;
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pDMAch->CConfig = 0x00;
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/* Assign Linker List Item value */
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pDMAch->CLLI = GPDMAChannelConfig->DMALLI;
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/* Set value to Channel Control Registers */
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switch (GPDMAChannelConfig->TransferType)
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{
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// Memory to memory
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case GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA:
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// Assign physical source and destination address
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pDMAch->CSrcAddr = GPDMAChannelConfig->SrcMemAddr;
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pDMAch->CDestAddr = GPDMAChannelConfig->DstMemAddr;
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pDMAch->CControl
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= GPDMA_DMACCxControl_TransferSize(GPDMAChannelConfig->TransferSize) \
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| GPDMA_DMACCxControl_SBSize(GPDMA_BSIZE_32) \
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| GPDMA_DMACCxControl_DBSize(GPDMA_BSIZE_32) \
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| GPDMA_DMACCxControl_SWidth(GPDMAChannelConfig->TransferWidth) \
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| GPDMA_DMACCxControl_DWidth(GPDMAChannelConfig->TransferWidth) \
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| GPDMA_DMACCxControl_SI \
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| GPDMA_DMACCxControl_DI \
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| GPDMA_DMACCxControl_I;
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break;
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// Memory to peripheral
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case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA:
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// Assign physical source
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pDMAch->CSrcAddr = GPDMAChannelConfig->SrcMemAddr;
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// Assign peripheral destination address
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pDMAch->CDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn];
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||
pDMAch->CControl
|
||
= GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
|
||
| GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
|
||
| GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
|
||
| GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
|
||
| GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
|
||
| GPDMA_DMACCxControl_DestTransUseAHBMaster1 \
|
||
| GPDMA_DMACCxControl_SI \
|
||
| GPDMA_DMACCxControl_I;
|
||
DestPeripheral = DMAMUX_Config(GPDMAChannelConfig->DstConn);
|
||
break;
|
||
// Peripheral to memory
|
||
case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA:
|
||
// Assign peripheral source address
|
||
pDMAch->CSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn];
|
||
// Assign memory destination address
|
||
pDMAch->CDestAddr = GPDMAChannelConfig->DstMemAddr;
|
||
pDMAch->CControl
|
||
= GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
|
||
| GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
|
||
| GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
|
||
| GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
|
||
| GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
|
||
| GPDMA_DMACCxControl_SrcTransUseAHBMaster1 \
|
||
| GPDMA_DMACCxControl_DI \
|
||
| GPDMA_DMACCxControl_I;
|
||
SrcPeripheral = DMAMUX_Config(GPDMAChannelConfig->SrcConn);
|
||
break;
|
||
// Peripheral to peripheral
|
||
case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA:
|
||
// Assign peripheral source address
|
||
pDMAch->CSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn];
|
||
// Assign peripheral destination address
|
||
pDMAch->CDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn];
|
||
pDMAch->CControl
|
||
= GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
|
||
| GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
|
||
| GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
|
||
| GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
|
||
| GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
|
||
| GPDMA_DMACCxControl_SrcTransUseAHBMaster1 \
|
||
| GPDMA_DMACCxControl_DestTransUseAHBMaster1 \
|
||
| GPDMA_DMACCxControl_I;
|
||
SrcPeripheral = DMAMUX_Config(GPDMAChannelConfig->SrcConn);
|
||
DestPeripheral = DMAMUX_Config(GPDMAChannelConfig->DstConn);
|
||
break;
|
||
|
||
case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL:
|
||
case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL:
|
||
case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL:
|
||
case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL:
|
||
//to be defined
|
||
// Do not support any more transfer type, return ERROR
|
||
default:
|
||
return ERROR;
|
||
}
|
||
|
||
/* Enable DMA channels, little endian */
|
||
LPC_GPDMA->CONFIG = GPDMA_DMACConfig_E;
|
||
while (!(LPC_GPDMA->CONFIG & GPDMA_DMACConfig_E));
|
||
|
||
// Configure DMA Channel, enable Error Counter and Terminate counter
|
||
pDMAch->CConfig = GPDMA_DMACCxConfig_IE | GPDMA_DMACCxConfig_ITC /*| GPDMA_DMACCxConfig_E*/ \
|
||
| GPDMA_DMACCxConfig_TransferType((uint32_t)GPDMAChannelConfig->TransferType) \
|
||
| GPDMA_DMACCxConfig_SrcPeripheral(SrcPeripheral) \
|
||
| GPDMA_DMACCxConfig_DestPeripheral(DestPeripheral);
|
||
|
||
return SUCCESS;
|
||
}
|
||
|
||
|
||
/*********************************************************************//**
|
||
* @brief Enable/Disable DMA channel
|
||
* @param[in] channelNum GPDMA channel, should be in range from 0 to 15
|
||
* @param[in] NewState New State of this command, should be:
|
||
* - ENABLE.
|
||
* - DISABLE.
|
||
* @return None
|
||
**********************************************************************/
|
||
void GPDMA_ChannelCmd(uint8_t channelNum, FunctionalState NewState)
|
||
{
|
||
LPC_GPDMACH_TypeDef *pDMAch;
|
||
|
||
// Get Channel pointer
|
||
pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[channelNum];
|
||
|
||
if (NewState == ENABLE) {
|
||
pDMAch->CConfig |= GPDMA_DMACCxConfig_E;
|
||
} else {
|
||
pDMAch->CConfig &= ~GPDMA_DMACCxConfig_E;
|
||
}
|
||
}
|
||
|
||
|
||
/*********************************************************************//**
|
||
* @brief Check if corresponding channel does have an active interrupt
|
||
* request or not
|
||
* @param[in] type type of status, should be:
|
||
* - GPDMA_STAT_INT :GPDMA Interrupt Status
|
||
* - GPDMA_STAT_INTTC :GPDMA Interrupt Terminal Count Request Status
|
||
* - GPDMA_STAT_INTERR :GPDMA Interrupt Error Status
|
||
* - GPDMA_STAT_RAWINTTC :GPDMA Raw Interrupt Terminal Count Status
|
||
* - GPDMA_STAT_RAWINTERR :GPDMA Raw Error Interrupt Status
|
||
* - GPDMA_STAT_ENABLED_CH :GPDMA Enabled Channel Status
|
||
* @param[in] channel GPDMA channel, should be in range from 0 to 7
|
||
* @return IntStatus status of DMA channel interrupt after masking
|
||
* Should be:
|
||
* - SET :the corresponding channel has no active interrupt request
|
||
* - RESET :the corresponding channel does have an active interrupt request
|
||
**********************************************************************/
|
||
IntStatus GPDMA_IntGetStatus(GPDMA_Status_Type type, uint8_t channel)
|
||
{
|
||
CHECK_PARAM(PARAM_GPDMA_STAT(type));
|
||
CHECK_PARAM(PARAM_GPDMA_CHANNEL(channel));
|
||
|
||
switch (type)
|
||
{
|
||
case GPDMA_STAT_INT: //check status of DMA channel interrupts
|
||
if (LPC_GPDMA->INTSTAT & (GPDMA_DMACIntStat_Ch(channel)))
|
||
return SET;
|
||
return RESET;
|
||
case GPDMA_STAT_INTTC: // check terminal count interrupt request status for DMA
|
||
if (LPC_GPDMA->INTTCSTAT & GPDMA_DMACIntTCStat_Ch(channel))
|
||
return SET;
|
||
return RESET;
|
||
case GPDMA_STAT_INTERR: //check interrupt status for DMA channels
|
||
if (LPC_GPDMA->INTERRSTAT & GPDMA_DMACIntTCClear_Ch(channel))
|
||
return SET;
|
||
return RESET;
|
||
case GPDMA_STAT_RAWINTTC: //check status of the terminal count interrupt for DMA channels
|
||
if (LPC_GPDMA->RAWINTERRSTAT & GPDMA_DMACRawIntTCStat_Ch(channel))
|
||
return SET;
|
||
return RESET;
|
||
case GPDMA_STAT_RAWINTERR: //check status of the error interrupt for DMA channels
|
||
if (LPC_GPDMA->RAWINTTCSTAT & GPDMA_DMACRawIntErrStat_Ch(channel))
|
||
return SET;
|
||
return RESET;
|
||
default: //check enable status for DMA channels
|
||
if (LPC_GPDMA->ENBLDCHNS & GPDMA_DMACEnbldChns_Ch(channel))
|
||
return SET;
|
||
return RESET;
|
||
}
|
||
}
|
||
|
||
/*********************************************************************//**
|
||
* @brief Clear one or more interrupt requests on DMA channels
|
||
* @param[in] type type of interrupt request, should be:
|
||
* - GPDMA_STATCLR_INTTC :GPDMA Interrupt Terminal Count Request Clear
|
||
* - GPDMA_STATCLR_INTERR :GPDMA Interrupt Error Clear
|
||
* @param[in] channel GPDMA channel, should be in range from 0 to 15
|
||
* @return None
|
||
**********************************************************************/
|
||
void GPDMA_ClearIntPending(GPDMA_StateClear_Type type, uint8_t channel)
|
||
{
|
||
CHECK_PARAM(PARAM_GPDMA_STATCLR(type));
|
||
CHECK_PARAM(PARAM_GPDMA_CHANNEL(channel));
|
||
|
||
if (type == GPDMA_STATCLR_INTTC) // clears the terminal count interrupt request on DMA channel
|
||
LPC_GPDMA->INTTCCLEAR = GPDMA_DMACIntTCClear_Ch(channel);
|
||
else // clear the error interrupt request
|
||
LPC_GPDMA->INTERRCLR = GPDMA_DMACIntErrClr_Ch(channel);
|
||
}
|
||
|
||
/**
|
||
* @}
|
||
*/
|
||
|
||
#endif /* _GPDMA */
|
||
|
||
/**
|
||
* @}
|
||
*/
|
||
|
||
/* --------------------------------- End Of File ------------------------------ */
|