507 lines
11 KiB
C
507 lines
11 KiB
C
/*
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* sys-dram.c
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*
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* Copyright(c) 2007-2018 Jianjun Jiang <8192542@qq.com>
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* Official site: http://xboot.org
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* Mobile phone: +86-18665388956
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* QQ: 8192542
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software Foundation,
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* Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <stdint.h>
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#include <f1c100s/reg-ccu.h>
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#include <f1c100s/reg-dram.h>
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#include <io.h>
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#define PLL_DDR_CLK (156000000)
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#define SDR_T_CAS (0x2)
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#define SDR_T_RAS (0x8)
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#define SDR_T_RCD (0x3)
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#define SDR_T_RP (0x3)
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#define SDR_T_WR (0x3)
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#define SDR_T_RFC (0xd)
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#define SDR_T_XSR (0xf9)
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#define SDR_T_RC (0xb)
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#define SDR_T_INIT (0x8)
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#define SDR_T_INIT_REF (0x7)
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#define SDR_T_WTR (0x2)
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#define SDR_T_RRD (0x2)
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#define SDR_T_XP (0x0)
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enum dram_type_t
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{
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DRAM_TYPE_SDR = 0,
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DRAM_TYPE_DDR = 1,
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DRAM_TYPE_MDDR = 2,
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};
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struct dram_para_t
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{
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uint32_t base; /* dram base address */
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uint32_t size; /* dram size (unit: MByte) */
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uint32_t clk; /* dram work clock (unit: MHz) */
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uint32_t access_mode; /* 0: interleave mode 1: sequence mode */
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uint32_t cs_num; /* dram chip count 1: one chip 2: two chip */
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uint32_t ddr8_remap; /* for 8bits data width DDR 0: normal 1: 8bits */
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enum dram_type_t sdr_ddr;
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uint32_t bwidth; /* dram bus width */
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uint32_t col_width; /* column address width */
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uint32_t row_width; /* row address width */
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uint32_t bank_size; /* dram bank count */
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uint32_t cas; /* dram cas */
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};
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static inline void sdelay(int loops)
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{
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__asm__ __volatile__ ("1:\n" "subs %0, %1, #1\n"
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"bne 1b":"=r" (loops):"0"(loops));
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}
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static void dram_delay(int ms)
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{
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sdelay(ms * 2 * 1000);
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}
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static int dram_initial(void)
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{
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unsigned int time = 0xffffff;
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write32(F1C100S_DRAM_BASE + DRAM_SCTLR, read32(F1C100S_DRAM_BASE + DRAM_SCTLR) | 0x1);
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while((read32(F1C100S_DRAM_BASE + DRAM_SCTLR) & 0x1) && time--)
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{
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if(time == 0)
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return 0;
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}
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return 1;
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}
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static int dram_delay_scan(void)
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{
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unsigned int time = 0xffffff;
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write32(F1C100S_DRAM_BASE + DRAM_DDLYR, read32(F1C100S_DRAM_BASE + DRAM_DDLYR) | 0x1);
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while((read32(F1C100S_DRAM_BASE + DRAM_DDLYR) & 0x1) && time--)
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{
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if(time == 0)
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return 0;
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}
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return 1;
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}
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static void dram_set_autofresh_cycle(uint32_t clk)
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{
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uint32_t val = 0;
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uint32_t row = 0;
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uint32_t temp = 0;
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row = read32(F1C100S_DRAM_BASE + DRAM_SCONR);
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row &= 0x1e0;
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row >>= 0x5;
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if(row == 0xc)
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{
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if(clk >= 1000000)
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{
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temp = clk + (clk >> 3) + (clk >> 4) + (clk >> 5);
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while(temp >= (10000000 >> 6))
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{
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temp -= (10000000 >> 6);
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val++;
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}
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}
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else
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{
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val = (clk * 499) >> 6;
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}
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}
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else if(row == 0xb)
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{
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if(clk >= 1000000)
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{
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temp = clk + (clk >> 3) + (clk >> 4) + (clk >> 5);
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while(temp >= (10000000 >> 7))
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{
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temp -= (10000000 >> 7);
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val++;
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}
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}
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else
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{
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val = (clk * 499) >> 5;
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}
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}
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write32(F1C100S_DRAM_BASE + DRAM_SREFR, val);
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}
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static int dram_para_setup(struct dram_para_t * para)
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{
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uint32_t val = 0;
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val = (para->ddr8_remap) |
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(0x1 << 1) |
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((para->bank_size >> 2) << 3) |
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((para->cs_num >> 1) << 4) |
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((para->row_width - 1) << 5) |
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((para->col_width - 1) << 9) |
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((para->sdr_ddr ? (para->bwidth >> 4) : (para->bwidth >> 5)) << 13) |
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(para->access_mode << 15) |
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(para->sdr_ddr << 16);
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write32(F1C100S_DRAM_BASE + DRAM_SCONR, val);
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write32(F1C100S_DRAM_BASE + DRAM_SCTLR, read32(F1C100S_DRAM_BASE + DRAM_SCTLR) | (0x1 << 19));
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return dram_initial();
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}
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static uint32_t dram_check_delay(uint32_t bwidth)
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{
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uint32_t dsize;
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uint32_t i,j;
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uint32_t num = 0;
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uint32_t dflag = 0;
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dsize = ((bwidth == 16) ? 4 : 2);
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for(i = 0; i < dsize; i++)
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{
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if(i == 0)
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dflag = read32(F1C100S_DRAM_BASE + DRAM_DRPTR0);
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else if(i == 1)
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dflag = read32(F1C100S_DRAM_BASE + DRAM_DRPTR1);
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else if(i == 2)
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dflag = read32(F1C100S_DRAM_BASE + DRAM_DRPTR2);
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else if(i == 3)
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dflag = read32(F1C100S_DRAM_BASE + DRAM_DRPTR3);
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for(j = 0; j < 32; j++)
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{
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if(dflag & 0x1)
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num++;
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dflag >>= 1;
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}
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}
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return num;
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}
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static int sdr_readpipe_scan(void)
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{
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uint32_t k = 0;
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for(k = 0; k < 32; k++)
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{
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write32(0x80000000 + 4 * k, k);
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}
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for(k = 0; k < 32; k++)
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{
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if(read32(0x80000000 + 4 * k) != k)
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return 0;
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}
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return 1;
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}
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static uint32_t sdr_readpipe_select(void)
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{
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uint32_t value = 0;
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uint32_t i = 0;
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for(i = 0; i < 8; i++)
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{
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write32(F1C100S_DRAM_BASE + DRAM_SCTLR, (read32(F1C100S_DRAM_BASE + DRAM_SCTLR) & (~(0x7 << 6))) | (i << 6));
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if(sdr_readpipe_scan())
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{
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value = i;
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return value;
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}
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}
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return value;
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}
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static uint32_t dram_check_type(struct dram_para_t * para)
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{
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uint32_t val = 0;
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uint32_t times = 0;
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uint32_t i;
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for(i = 0; i < 8; i++)
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{
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val = read32(F1C100S_DRAM_BASE + DRAM_SCTLR);
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val &= ~(0x7 << 6);
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val |= (i << 6);
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write32(F1C100S_DRAM_BASE + DRAM_SCTLR, val);
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dram_delay_scan();
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if(read32(F1C100S_DRAM_BASE + DRAM_DDLYR) & 0x30)
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times++;
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}
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if(times == 8)
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{
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para->sdr_ddr = DRAM_TYPE_SDR;
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return 0;
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}
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else
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{
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para->sdr_ddr = DRAM_TYPE_DDR;
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return 1;
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}
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}
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static uint32_t dram_scan_readpipe(struct dram_para_t * para)
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{
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uint32_t i, rp_best = 0, rp_val = 0;
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uint32_t val = 0;
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uint32_t readpipe[8];
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if(para->sdr_ddr == DRAM_TYPE_DDR)
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{
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for(i = 0; i < 8; i++)
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{
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val = read32(F1C100S_DRAM_BASE + DRAM_SCTLR);
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val &= ~(0x7 << 6);
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val |= (i << 6);
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write32(F1C100S_DRAM_BASE + DRAM_SCTLR, val);
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dram_delay_scan();
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readpipe[i] = 0;
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if((((read32(F1C100S_DRAM_BASE + DRAM_DDLYR) >> 4) & 0x3) == 0x0) &&
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(((read32(F1C100S_DRAM_BASE + DRAM_DDLYR) >> 4) & 0x1) == 0x0))
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{
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readpipe[i] = dram_check_delay(para->bwidth);
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}
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if(rp_val < readpipe[i])
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{
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rp_val = readpipe[i];
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rp_best = i;
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}
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}
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val = read32(F1C100S_DRAM_BASE + DRAM_SCTLR);
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val &= ~(0x7 << 6);
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val |= (rp_best << 6);
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write32(F1C100S_DRAM_BASE + DRAM_SCTLR, val);
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dram_delay_scan();
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}
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else
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{
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val = read32(F1C100S_DRAM_BASE + DRAM_SCONR);
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val &= (~(0x1 << 16));
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val &= (~(0x3 << 13));
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write32(F1C100S_DRAM_BASE + DRAM_SCONR, val);
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rp_best = sdr_readpipe_select();
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val = read32(F1C100S_DRAM_BASE + DRAM_SCTLR);
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val &= ~(0x7 << 6);
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val |= (rp_best << 6);
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write32(F1C100S_DRAM_BASE + DRAM_SCTLR, val);
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}
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return 0;
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}
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static uint32_t dram_get_dram_size(struct dram_para_t * para)
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{
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uint32_t colflag = 10, rowflag = 13;
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uint32_t i = 0;
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uint32_t val1 = 0;
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uint32_t count = 0;
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uint32_t addr1, addr2;
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para->col_width = colflag;
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para->row_width = rowflag;
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dram_para_setup(para);
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dram_scan_readpipe(para);
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for(i = 0; i < 32; i++)
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{
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*((uint32_t *)(0x80000200 + i)) = 0x11111111;
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*((uint32_t *)(0x80000600 + i)) = 0x22222222;
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}
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for(i = 0; i < 32; i++)
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{
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val1 = *((uint32_t *)(0x80000200 + i));
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if(val1 == 0x22222222)
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count++;
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}
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if(count == 32)
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{
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colflag = 9;
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}
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else
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{
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colflag = 10;
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}
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count = 0;
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para->col_width = colflag;
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para->row_width = rowflag;
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dram_para_setup(para);
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if(colflag == 10)
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{
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addr1 = 0x80400000;
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addr2 = 0x80c00000;
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}
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else
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{
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addr1 = 0x80200000;
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addr2 = 0x80600000;
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}
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for(i = 0; i < 32; i++)
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{
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*((uint32_t *)(addr1 + i)) = 0x33333333;
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*((uint32_t *)(addr2 + i)) = 0x44444444;
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}
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for(i = 0; i < 32; i++)
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{
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val1 = *((uint32_t *)(addr1 + i));
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if(val1 == 0x44444444)
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{
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count++;
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}
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}
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if(count == 32)
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{
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rowflag = 12;
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}
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else
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{
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rowflag = 13;
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}
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para->col_width = colflag;
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para->row_width = rowflag;
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if(para->row_width != 13)
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{
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para->size = 16;
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}
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else if(para->col_width == 10)
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{
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para->size = 64;
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}
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else
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{
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para->size = 32;
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}
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dram_set_autofresh_cycle(para->clk);
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para->access_mode = 0;
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dram_para_setup(para);
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return 0;
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}
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static int dram_init(struct dram_para_t * para)
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{
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uint32_t val = 0;
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uint32_t i;
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write32(0x01c20800 + 0x24, read32(0x01c20800 + 0x24) | (0x7 << 12));
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dram_delay(5);
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if(((para->cas) >> 3) & 0x1)
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{
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write32(0x01c20800 + 0x2c4, read32(0x01c20800 + 0x2c4) | (0x1 << 23) | (0x20 << 17));
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}
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if((para->clk >= 144) && (para->clk <= 180))
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{
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write32(0x01c20800 + 0x2c0, 0xaaa);
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}
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if(para->clk >= 180)
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{
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write32(0x01c20800 + 0x2c0, 0xfff);
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}
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if((para->clk) <= 96)
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{
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val = (0x1 << 0) | (0x0 << 4) | (((para->clk * 2) / 12 - 1) << 8) | (0x1u << 31);
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}
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else
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{
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val = (0x0 << 0) | (0x0 << 4) | (((para->clk * 2) / 24 - 1) << 8) | (0x1u << 31);
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}
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if(para->cas & (0x1 << 4))
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{
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write32(F1C100S_CCU_BASE + CCU_PLL_DDR0_PAT, 0xd1303333);
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}
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else if(para->cas & (0x1 << 5))
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{
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write32(F1C100S_CCU_BASE + CCU_PLL_DDR0_PAT, 0xcce06666);
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}
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else if(para->cas & (0x1 << 6))
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{
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write32(F1C100S_CCU_BASE + CCU_PLL_DDR0_PAT, 0xc8909999);
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}
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else if(para->cas & (0x1 << 7))
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{
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write32(F1C100S_CCU_BASE + CCU_PLL_DDR0_PAT, 0xc440cccc);
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}
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if(para->cas & (0xf << 4))
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{
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val |= 0x1 << 24;
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}
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write32(F1C100S_CCU_BASE + CCU_PLL_DDR_CTRL, val);
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write32(F1C100S_CCU_BASE + CCU_PLL_DDR_CTRL, read32(F1C100S_CCU_BASE + CCU_PLL_DDR_CTRL) | (0x1 << 20));
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while((read32(F1C100S_CCU_BASE + CCU_PLL_DDR_CTRL) & (1 << 28)) == 0);
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dram_delay(5);
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write32(F1C100S_CCU_BASE + CCU_BUS_CLK_GATE0, read32(F1C100S_CCU_BASE + CCU_BUS_CLK_GATE0) | (0x1 << 14));
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write32(F1C100S_CCU_BASE + CCU_BUS_SOFT_RST0, read32(F1C100S_CCU_BASE + CCU_BUS_SOFT_RST0) & ~(0x1 << 14));
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for(i = 0; i < 10; i++)
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continue;
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write32(F1C100S_CCU_BASE + CCU_BUS_SOFT_RST0, read32(F1C100S_CCU_BASE + CCU_BUS_SOFT_RST0) | (0x1 << 14));
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val = read32(0x01c20800 + 0x2c4);
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(para->sdr_ddr == DRAM_TYPE_DDR) ? (val |= (0x1 << 16)) : (val &= ~(0x1 << 16));
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write32(0x01c20800 + 0x2c4, val);
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val = (SDR_T_CAS << 0) | (SDR_T_RAS << 3) | (SDR_T_RCD << 7) | (SDR_T_RP << 10) | (SDR_T_WR << 13) | (SDR_T_RFC << 15) | (SDR_T_XSR << 19) | (SDR_T_RC << 28);
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write32(F1C100S_DRAM_BASE + DRAM_STMG0R, val);
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val = (SDR_T_INIT << 0) | (SDR_T_INIT_REF << 16) | (SDR_T_WTR << 20) | (SDR_T_RRD << 22) | (SDR_T_XP << 25);
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write32(F1C100S_DRAM_BASE + DRAM_STMG1R, val);
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dram_para_setup(para);
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dram_check_type(para);
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val = read32(0x01c20800 + 0x2c4);
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(para->sdr_ddr == DRAM_TYPE_DDR) ? (val |= (0x1 << 16)) : (val &= ~(0x1 << 16));
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write32(0x01c20800 + 0x2c4, val);
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dram_set_autofresh_cycle(para->clk);
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dram_scan_readpipe(para);
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dram_get_dram_size(para);
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for(i = 0; i < 128; i++)
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{
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*((volatile uint32_t *)(para->base + 4 * i)) = para->base + 4 * i;
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}
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for(i = 0; i < 128; i++)
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{
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if(*((volatile uint32_t *)(para->base + 4 * i)) != (para->base + 4 * i))
|
|
return 0;
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
void sys_dram_init(void)
|
|
{
|
|
struct dram_para_t para;
|
|
uint32_t * dsz = (void *)0x0000005c;
|
|
|
|
para.base = 0x80000000;
|
|
para.size = 32;
|
|
para.clk = PLL_DDR_CLK / 1000000;
|
|
para.access_mode = 1;
|
|
para.cs_num = 1;
|
|
para.ddr8_remap = 0;
|
|
para.sdr_ddr = DRAM_TYPE_DDR;
|
|
para.bwidth = 16;
|
|
para.col_width = 10;
|
|
para.row_width = 13;
|
|
para.bank_size = 4;
|
|
para.cas = 0x3;
|
|
|
|
if((dsz[0] >> 24) == 'X')
|
|
return;
|
|
if(dram_init(¶))
|
|
dsz[0] = (((uint32_t)'X') << 24) | (para.size << 0);
|
|
}
|