102 lines
3.6 KiB
C
102 lines
3.6 KiB
C
/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2021, Ha Thach (tinyusb.org)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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#ifndef _CI_HS_IMXRT_H_
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#define _CI_HS_IMXRT_H_
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#include "fsl_device_registers.h"
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#if !defined(USB1_BASE) && defined(USB_OTG1_BASE)
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#define USB1_BASE USB_OTG1_BASE
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#endif
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#if !defined(USB2_BASE) && defined(USB_OTG2_BASE)
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#define USB2_BASE USB_OTG2_BASE
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#endif
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// RT1040 calls its only USB USB_OTG (no 1)
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#if defined(MIMXRT1042_SERIES)
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#define USB_OTG1_IRQn USB_OTG_IRQn
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#endif
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static const ci_hs_controller_t _ci_controller[] =
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{
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// RT1010 and RT1020 only has 1 USB controller
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#if FSL_FEATURE_SOC_USBHS_COUNT == 1
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{ .reg_base = USB_BASE , .irqnum = USB_OTG1_IRQn }
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#else
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{ .reg_base = USB1_BASE, .irqnum = USB_OTG1_IRQn},
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{ .reg_base = USB2_BASE, .irqnum = USB_OTG2_IRQn}
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#endif
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};
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#define CI_HS_REG(_port) ((ci_hs_regs_t*) _ci_controller[_port].reg_base)
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//------------- DCD -------------//
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#define CI_DCD_INT_ENABLE(_p) NVIC_EnableIRQ (_ci_controller[_p].irqnum)
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#define CI_DCD_INT_DISABLE(_p) NVIC_DisableIRQ(_ci_controller[_p].irqnum)
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//------------- HCD -------------//
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#define CI_HCD_INT_ENABLE(_p) NVIC_EnableIRQ (_ci_controller[_p].irqnum)
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#define CI_HCD_INT_DISABLE(_p) NVIC_DisableIRQ(_ci_controller[_p].irqnum)
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//------------- DCache -------------//
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TU_ATTR_ALWAYS_INLINE static inline bool imxrt_is_cache_mem(uintptr_t addr) {
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return !(0x20000000 <= addr && addr < 0x20100000);
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}
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TU_ATTR_ALWAYS_INLINE static inline bool imxrt_dcache_clean(void const* addr, uint32_t data_size) {
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const uintptr_t addr32 = (uintptr_t) addr;
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if (imxrt_is_cache_mem(addr32)) {
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TU_ASSERT(tu_is_aligned32(addr32));
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SCB_CleanDCache_by_Addr((uint32_t *) addr32, (int32_t) data_size);
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}
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return true;
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}
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TU_ATTR_ALWAYS_INLINE static inline bool imxrt_dcache_invalidate(void const* addr, uint32_t data_size) {
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const uintptr_t addr32 = (uintptr_t) addr;
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if (imxrt_is_cache_mem(addr32)) {
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// Invalidating does not push cached changes back to RAM so we need to be
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// *very* careful when we do it. If we're not aligned, then we risk resetting
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// values back to their RAM state.
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TU_ASSERT(tu_is_aligned32(addr32));
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SCB_InvalidateDCache_by_Addr((void*) addr32, (int32_t) data_size);
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}
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return true;
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}
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TU_ATTR_ALWAYS_INLINE static inline bool imxrt_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
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const uintptr_t addr32 = (uintptr_t) addr;
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if (imxrt_is_cache_mem(addr32)) {
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TU_ASSERT(tu_is_aligned32(addr32));
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SCB_CleanInvalidateDCache_by_Addr((uint32_t *) addr32, (int32_t) data_size);
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}
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return true;
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}
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#endif
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