verilog/make.py

import os
import sys


TARGET="wave"

SRC = ["testbench.v"]

INC = ['verilog']

IVER="iverilog"
VVP="vvp"
GTKWAVE="gtkwave"

for i in range(len(INC)):
  tmp=os.path.join(os.path.curdir,INC[i])
  tmp=os.path.abspath(tmp).replace('/','\\')
  INC[i]='-I '+tmp

for i in range(len(SRC)):
  tmp=os.path.join(os.path.curdir,SRC[i])
  tmp=os.path.abspath(tmp).replace('/','\\')
  SRC[i]=tmp


def make():
  cmd=' '.join([IVER,'-o',TARGET]+INC+SRC)
  if(os.system(cmd)):
    sys.exit(-1)
  cmd=' '.join([VVP,'-n',TARGET,'lxt2'])
  if(os.system(cmd)):
    sys.exit(-1)
  cmd=' '.join([GTKWAVE,TARGET+'.vcd'])
  if(os.system(cmd)):
    sys.exit(-1)

if __name__ == "__main__":
  make()