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verilog/make.py

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Python
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2024-12-30 16:19:10 +08:00
import os
import sys
TARGET="wave"
SRC = ["testbench.v"]
INC = []
IVER="iverilog"
VVP="vvp"
GTKWAVE="gtkwave"
def make():
cmd=' '.join([IVER,'-o',TARGET]+SRC)
if(os.system(cmd)):
sys.exit(-1)
cmd=' '.join([VVP,'-n',TARGET,'lxt2'])
if(os.system(cmd)):
sys.exit(-1)
cmd=' '.join([GTKWAVE,TARGET+'.vcd'])
if(os.system(cmd)):
sys.exit(-1)
if __name__ == "__main__":
make()