andy/verilog
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
6efb3b0473fc2c88fcd84300f7dc449e5bef5b4e
verilog/ReadMe.txt

7 lines
125 B
Plaintext
Raw Normal View History

实现根据时钟来自增计数器
2024-12-30 16:19:10 +08:00
2024.12.30
实现一个改变时钟电平的基本电路
实现mem
2025-03-11 17:54:18 +08:00
每个时钟周期计数器加1
2025.3.11
实现内存模块
Reference in New Issue Copy Permalink