From 067f637ab8de62a9835d9fd0de3fada745e60fcd Mon Sep 17 00:00:00 2001
From: ranchuan <ran.chuan@acp-ic.com>
Date: Mon, 30 Dec 2024 19:32:43 +0800
Subject: [PATCH] =?UTF-8?q?=E8=AF=BB=E5=8F=96=E5=A4=96=E9=83=A8=E6=96=87?=
 =?UTF-8?q?=E4=BB=B6?=
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---
 flash_data.txt |  1 +
 main_module.v  | 10 ++++++++--
 testbench.v    | 18 ++++++++++++++++++
 3 files changed, 27 insertions(+), 2 deletions(-)
 create mode 100644 flash_data.txt

diff --git a/flash_data.txt b/flash_data.txt
new file mode 100644
index 0000000..f6b3034
--- /dev/null
+++ b/flash_data.txt
@@ -0,0 +1 @@
+01 02 03 04 05 06 07 08 09 10
\ No newline at end of file
diff --git a/main_module.v b/main_module.v
index 3b3c9b0..7935529 100644
--- a/main_module.v
+++ b/main_module.v
@@ -5,11 +5,13 @@
 module test (
   input clk,
   input rst,
+  input [7:0] data,
   output dout,
+  output reg [7:0] data_addr,
   // 声明变量 如果不指定变量类型 则默认是wire类型
   output reg [31:0] sum
 );
-
+  reg [31:0] count;
   assign dout = ~clk;
 
 
@@ -18,9 +20,13 @@ module test (
   always @(posedge clk or rst) begin
     if(rst==0) begin
       sum <= 0;
+      count <= 0;
+      data_addr <=0;
     end
     else begin
-      sum <= sum+1;
+      count <= count+1;
+      sum <= data*2;
+      data_addr <= count[7:0];
     end
   end
 
diff --git a/testbench.v b/testbench.v
index 959fb63..b2a02fb 100644
--- a/testbench.v
+++ b/testbench.v
@@ -7,8 +7,12 @@
 module testbench();
   reg clk;
   reg rst;
+  reg [7:0] data;
   wire dout;
   wire [31:0] sum;
+  wire [7:0] data_addr;
+  // 定义一个存储空间 8位 256个字节
+  reg [7:0] flash_mem[255:0];
   // 指定参数
   parameter CYCLE = 2;
   parameter END_TIME = 200;
@@ -17,7 +21,9 @@ module testbench();
   test mod(
     .clk(clk),
     .rst(rst),
+    .data(data),
     .dout(dout),
+    .data_addr(data_addr),
     .sum(sum)
   );
 
@@ -26,8 +32,15 @@ module testbench();
   initial begin
     $dumpfile("wave.vcd");
     $dumpvars(0,testbench);
+    // 把文件中的16进制数据填充到mem
+    $readmemh("flash_data.txt",flash_mem);
   end
 
+  //显示数组的10个值
+  // initial begin
+  //     $display("yyyyy %d: %h", 0, flash_mem[0]);
+  // end
+
   // 寄存器初始化，只有初始化之后才会产生波形
   initial begin
     clk = 0;
@@ -42,6 +55,11 @@ module testbench();
     #(CYCLE / 2) clk = ~clk;
   end
 
+  always @(posedge clk) begin
+    data <= flash_mem[data_addr];
+    $display("yyyyy %d: %h", data_addr, flash_mem[data_addr]);
+end
+
   // 在END_TIME个时钟周期之后结束
   initial begin
     #END_TIME;