实现mem

This commit is contained in:
ranchuan
2025-03-11 17:54:18 +08:00
parent 067f637ab8
commit 6efb3b0473
5 changed files with 108 additions and 29 deletions

15
make.py
View File

@@ -6,14 +6,25 @@ TARGET="wave"
SRC = ["testbench.v"]
INC = []
INC = ['verilog']
IVER="iverilog"
VVP="vvp"
GTKWAVE="gtkwave"
for i in range(len(INC)):
tmp=os.path.join(os.path.curdir,INC[i])
tmp=os.path.abspath(tmp).replace('/','\\')
INC[i]='-I '+tmp
for i in range(len(SRC)):
tmp=os.path.join(os.path.curdir,SRC[i])
tmp=os.path.abspath(tmp).replace('/','\\')
SRC[i]=tmp
def make():
cmd=' '.join([IVER,'-o',TARGET]+SRC)
cmd=' '.join([IVER,'-o',TARGET]+INC+SRC)
if(os.system(cmd)):
sys.exit(-1)
cmd=' '.join([VVP,'-n',TARGET,'lxt2'])