From dcb6b4b7ec2f13d54df34d8f45d33a7d3f4a2c56 Mon Sep 17 00:00:00 2001
From: ranchuan <ran.chuan@acp-ic.com>
Date: Mon, 30 Dec 2024 16:19:10 +0800
Subject: [PATCH] =?UTF-8?q?=E5=AE=9E=E7=8E=B0=E6=A0=B9=E6=8D=AE=E6=97=B6?=
 =?UTF-8?q?=E9=92=9F=E6=9D=A5=E8=87=AA=E5=A2=9E=E8=AE=A1=E6=95=B0=E5=99=A8?=
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---
 .gitignore    |  2 ++
 ReadMe.txt    |  5 +++++
 main_module.v | 27 +++++++++++++++++++++++++++
 make.py       | 27 +++++++++++++++++++++++++++
 testbench.v   | 51 +++++++++++++++++++++++++++++++++++++++++++++++++++
 5 files changed, 112 insertions(+)
 create mode 100644 .gitignore
 create mode 100644 ReadMe.txt
 create mode 100644 main_module.v
 create mode 100644 make.py
 create mode 100644 testbench.v

diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..a6f126f
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,2 @@
+wave
+wave.vcd
\ No newline at end of file
diff --git a/ReadMe.txt b/ReadMe.txt
new file mode 100644
index 0000000..7c6c107
--- /dev/null
+++ b/ReadMe.txt
@@ -0,0 +1,5 @@
+
+
+2024.12.30
+  实现一个改变时钟电平的基本电路
+  每个时钟周期计数器加1
\ No newline at end of file
diff --git a/main_module.v b/main_module.v
new file mode 100644
index 0000000..3b3c9b0
--- /dev/null
+++ b/main_module.v
@@ -0,0 +1,27 @@
+
+
+
+
+module test (
+  input clk,
+  input rst,
+  output dout,
+  // 声明变量 如果不指定变量类型 则默认是wire类型
+  output reg [31:0] sum
+);
+
+  assign dout = ~clk;
+
+
+  // 在时钟的上升沿开始计算
+  // 对时钟上升沿或rst电平敏感
+  always @(posedge clk or rst) begin
+    if(rst==0) begin
+      sum <= 0;
+    end
+    else begin
+      sum <= sum+1;
+    end
+  end
+
+endmodule
\ No newline at end of file
diff --git a/make.py b/make.py
new file mode 100644
index 0000000..f22c663
--- /dev/null
+++ b/make.py
@@ -0,0 +1,27 @@
+import os
+import sys
+
+
+TARGET="wave"
+
+SRC = ["testbench.v"]
+
+INC = []
+
+IVER="iverilog"
+VVP="vvp"
+GTKWAVE="gtkwave"
+
+def make():
+  cmd=' '.join([IVER,'-o',TARGET]+SRC)
+  if(os.system(cmd)):
+    sys.exit(-1)
+  cmd=' '.join([VVP,'-n',TARGET,'lxt2'])
+  if(os.system(cmd)):
+    sys.exit(-1)
+  cmd=' '.join([GTKWAVE,TARGET+'.vcd'])
+  if(os.system(cmd)):
+    sys.exit(-1)
+
+if __name__ == "__main__":
+  make()
\ No newline at end of file
diff --git a/testbench.v b/testbench.v
new file mode 100644
index 0000000..959fb63
--- /dev/null
+++ b/testbench.v
@@ -0,0 +1,51 @@
+
+// 时间尺度 以1ns为时钟单位 / 1ns为时钟精度
+`timescale 1ns/1ns
+// 包含文件 main_module.v 编译的时候就不需要指定这个文件了
+`include "main_module.v"
+// 定义模块 此模块没有输入输出
+module testbench();
+  reg clk;
+  reg rst;
+  wire dout;
+  wire [31:0] sum;
+  // 指定参数
+  parameter CYCLE = 2;
+  parameter END_TIME = 200;
+
+  // 实例化模块
+  test mod(
+    .clk(clk),
+    .rst(rst),
+    .dout(dout),
+    .sum(sum)
+  );
+
+  // 初始化块 此块用于生成波形文件
+  // initial 语句为仿真语句，通常在testbench中使用
+  initial begin
+    $dumpfile("wave.vcd");
+    $dumpvars(0,testbench);
+  end
+
+  // 寄存器初始化，只有初始化之后才会产生波形
+  initial begin
+    clk = 0;
+    rst = 0;
+  end
+  initial begin
+    #5 rst = 1;
+  end
+
+  // 每隔一个时钟周期取反
+  always  begin
+    #(CYCLE / 2) clk = ~clk;
+  end
+
+  // 在END_TIME个时钟周期之后结束
+  initial begin
+    #END_TIME;
+    $stop;
+  end
+
+endmodule