From f52af2470e5c8c31fb50d0aa40a97fba951cb809 Mon Sep 17 00:00:00 2001
From: ranchuan <ran.chuan@acp-ic.com>
Date: Tue, 11 Mar 2025 18:36:01 +0800
Subject: [PATCH] =?UTF-8?q?=E5=A2=9E=E5=8A=A0data=E6=95=B0=E6=8D=AE?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 flash_data.txt |  7 ++++++-
 main_module.v  | 33 ---------------------------------
 testbench.v    |  4 ++--
 3 files changed, 8 insertions(+), 36 deletions(-)
 delete mode 100644 main_module.v

diff --git a/flash_data.txt b/flash_data.txt
index f6b3034..4960223 100644
--- a/flash_data.txt
+++ b/flash_data.txt
@@ -1 +1,6 @@
-01 02 03 04 05 06 07 08 09 10
\ No newline at end of file
+01 02 03 04 05 06 07 08 09 10
+11 12 13 14 15 16 17 18 19 20
+21 22 23 24 25 26 27 28 29 30
+31 32 33 34 35 36 37 38 39 40
+41 42 43 44 45 46 47 48 49 50
+51 52 53 54 55 56 57 58 59 60
\ No newline at end of file
diff --git a/main_module.v b/main_module.v
deleted file mode 100644
index 7935529..0000000
--- a/main_module.v
+++ /dev/null
@@ -1,33 +0,0 @@
-
-
-
-
-module test (
-  input clk,
-  input rst,
-  input [7:0] data,
-  output dout,
-  output reg [7:0] data_addr,
-  // 声明变量 如果不指定变量类型 则默认是wire类型
-  output reg [31:0] sum
-);
-  reg [31:0] count;
-  assign dout = ~clk;
-
-
-  // 在时钟的上升沿开始计算
-  // 对时钟上升沿或rst电平敏感
-  always @(posedge clk or rst) begin
-    if(rst==0) begin
-      sum <= 0;
-      count <= 0;
-      data_addr <=0;
-    end
-    else begin
-      count <= count+1;
-      sum <= data*2;
-      data_addr <= count[7:0];
-    end
-  end
-
-endmodule
\ No newline at end of file
diff --git a/testbench.v b/testbench.v
index 5c64d40..1957880 100644
--- a/testbench.v
+++ b/testbench.v
@@ -30,8 +30,8 @@ module testbench();
   mem mem_mod(
     .clk(clk),
     .rst(rst),
-    .write_en(1'b1),
-    .read_en(1'b0),
+    .write_en(1'b0),
+    .read_en(1'b1),
     .data_in(data),
     .addr(sum[7:0]),
     .data_out(read_data)