33 lines
566 B
Verilog
33 lines
566 B
Verilog
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module test (
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input clk,
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input rst,
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input [7:0] data,
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output dout,
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output reg [7:0] data_addr,
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// 声明变量 如果不指定变量类型 则默认是wire类型
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output reg [31:0] sum
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);
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reg [31:0] count;
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assign dout = ~clk;
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// 在时钟的上升沿开始计算
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// 对时钟上升沿或rst电平敏感
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always @(posedge clk or rst) begin
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if(rst==0) begin
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sum <= 0;
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count <= 0;
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data_addr <=0;
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end
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else begin
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count <= count+1;
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sum <= data*2;
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data_addr <= count[7:0];
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end
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end
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endmodule |