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ranchuan f52af2470e 增加data数据
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verilog
实现mem
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.gitignore
实现根据时钟来自增计数器
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flash_data.txt
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make.py
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ReadMe.txt
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testbench.v
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ReadMe.txt 


2024.12.30
  实现一个改变时钟电平的基本电路
  每个时钟周期计数器加1
2025.3.11
  实现内存模块
Description
verilog学习
Readme 32 KiB
Languages
Verilog 77.9%
Python 22.1%